Active
RoHS Compliant
Lead-free

S26KL128SDABHN030

Data Sheet
package
software

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

S26KL128SDABHN030
S26KL128SDABHN030
Data Sheet

Product details

  • Bus Width
    x8
  • Density
    128 MBit
  • Family
    KL-S
  • Initial Access Time
    96 ns
  • Interface Bandwidth
    200 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    - / 100
  • Interfaces
    HYPERBUS
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 125 °C
  • Operating Voltage range
    2.7 V to 3.6 V
  • Operating Voltage
    3 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2035
  • Qualification
    Industrial
  • Technology
    HYPERFLASH
Recommended
OPN
S26KL128SDABHN030
Product Status active
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 338
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 338
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
The S26KL128SDABHN030 is a 128 Mb (16 MB) 3.0 V HYPERFLASH™ NOR memory with a HYPERBUS™ DDR interface, enabling high-speed data transfers up to 333 MBps. It features an 8-bit data bus, 100 MHz clock at 3.0 V, 64 uniform 256-KB sectors, 100,000 program/erase cycles endurance, and 20-year data retention. AEC-Q100 Grade 2 qualification (–40°C to +105°C), ECC, CRC, advanced sector protection, and low-power modes ensure reliability in automotive and industrial environments.

Features

  • 8-bit data bus
  • HYPERBUS™ interface
  • Up to 333 MBps sustained read throughput
  • DDR: two data transfers per clock
  • 166 MHz clock rate at 1.8 V
  • 100 MHz clock rate at 3.0 V
  • 96 ns initial random read access time
  • Configurable burst lengths: 16/32/64 bytes
  • Low power modes: standby 25 µA, deep
  • ECC: 1-bit correction, 2-bit detection
  • Hardware CRC calculation
  • Secure silicon region (1024-byte OTP)

Benefits

  • Fast data access for high-performance systems
  • Flexible interface supports diverse designs
  • High-speed DDR improves throughput
  • Multiple burst lengths optimize transfers
  • Low power modes extend battery life
  • ECC ensures data integrity
  • CRC detects transmission errors
  • Secure region enables device authentication
  • Quick random access reduces latency
  • 8-bit bus simplifies integration
  • Configurable output drive for signal tuning
  • Reliable operation in harsh environments

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }