Active and preferred
RoHS Compliant
Lead-free

S26HL02GTFGBHV050

Data Sheet
package

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S26HL02GTFGBHV050
S26HL02GTFGBHV050
Data Sheet

Product details

  • Classification
    No Certification
  • Density
    2048 MBit
  • Family
    HL-T
  • Interface Frequency (SDR/DDR) (MHz)
    - / 133
  • Interfaces
    HYPERBUS
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 105 °C
  • Operating Voltage range
    2.7 V to 3.6 V
  • Operating Voltage
    3 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2037
  • Qualification
    Industrial
Recommended
OPN
S26HL02GTFGBHV050
Product Status active and preferred
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-24801)
Packing Size 2600
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-24801)
Packing Size 2600
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
The S26HL02GTFGBHV050 is a 2 Gb (2048 Mbit) SEMPER™ NOR Flash MCP for code and data storage, using a HYPERBUS™ (JESD251 xSPI) DDR interface up to 133 MHz (266 MBps) plus legacy (x1) SPI. It operates from 2.7 V to 3.6 V over -40°C to 105°C and supports wrapped or linear burst reads, uniform or hybrid 256 KB/4 KB sectors, a 256/512-byte page program buffer, and a 1024-byte OTP secure silicon region (SSR).

Features

  • 45-nm MIRRORBIT™ stores 2 bits/cell
  • JEDEC JESD251 xSPI compliant
  • HYPERBUS x8 DDR, DS read strobe
  • Legacy x1 SPI mode supported
  • Default boot: SPI x1 or HYPERBUS x8
  • Wrapped or linear burst reads
  • Auto fetch next page in linear burst
  • 256 B or 512 B program buffer option
  • OTP Secure Silicon Region 1024 B
  • Interface CRC for link error detect
  • Array CRC + ECC SECDED protection
  • Advanced per-sector protection

Benefits

  • Higher density in same die area
  • Easier host compatibility via xSPI
  • Simplifies high-speed read capture
  • Works with existing SPI controllers
  • Flexible boot for multiple platforms
  • Optimizes reads for MCU/XIP access
  • Sustained bandwidth for streaming
  • Shorter program time, higher thruput
  • Protects keys and device identity
  • Detects bus faults for safer comms
  • Improves data integrity in field
  • Prevents unauthorized sector writes

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

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