Active and preferred
RoHS Compliant
Lead-free

S25HL512TDPBHI010

Data Sheet
package
board
ea.
in stock

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S25HL512TDPBHI010
S25HL512TDPBHI010
ea.
Data Sheet

Product details

  • Density
    512 MBit
  • Family
    HL-T
  • Interface Bandwidth
    66 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    133 / 66
  • Interfaces
    Quad SPI
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    2.7 V to 3.6 V
  • Operating Voltage
    3 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2037
  • Qualification
    Industrial
Recommended
OPN
S25HL512TDPBHI010
Product Status active and preferred
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 338
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 338
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
S25HL512TDPBHI010 is a 512 Mbit SEMPER™ HL-T NOR flash for code and data storage in industrial embedded systems. It supports Quad SPI up to 133 MHz SDR and 66 MHz DDR (66 MByte/s) from a 2.7 V to 3.6 V supply over -40°C to +85°C. Built-in ECC (SECDED), CRC data integrity check, Endurance Flex wear leveling, SafeBoot, AutoBoot, and 1024-byte OTP SSR help improve data reliability and availability.

Features

  • 45-nm MIRRORBIT™ 2 bits per cell
  • Uniform or hybrid sector architecture
  • 256 KB sectors plus 32 x 4 KB sectors
  • 256 B or 512 B program buffer
  • Quad SPI: 1-1-4, 1-4-4, 4-4-4
  • Quad SPI DDR read up to 102 MBps
  • Hamming ECC on 16-byte data units
  • SECDED: correct 1-bit, detect 2-bit
  • Memory-array data integrity CRC
  • Endurance Flex wear leveling
  • ASP: DYB/PPB per-sector protection
  • 1024-byte SSR with 32 lock regions

Benefits

  • Higher density lowers board area
  • Match boot+data layout to MCU needs
  • Small sectors enable fine updates
  • Faster writes cut update time
  • Flexible host interface support
  • High read rate speeds code fetch
  • ECC boosts data reliability in field
  • Detects double-bit faults for safety
  • CRC flags corrupted reads early
  • Wear leveling extends flash life
  • Per-sector locks prevent tampering
  • SSR enables IDs and secure storage

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }