Active and preferred
RoHS Compliant
Lead-free

S25FS512SDSMFI011

Data Sheet
package
software
ea.
in stock

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S25FS512SDSMFI011
S25FS512SDSMFI011
ea.
Data Sheet

Product details

  • Density
    512 MBit
  • Family
    FS-S
  • Interface Bandwidth
    80 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    133 / 80
  • Interfaces
    Quad SPI
  • Lead Ball Finish
    Matte Tin Plating
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    1.7 V to 2 V
  • Operating Voltage
    1.8 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2035
  • Qualification
    Industrial
Recommended
OPN
S25FS512SDSMFI011
Product Status active and preferred
Infineon Package
PG-DSO-16
Package Name SOIC-16 (002-15547)
Packing Size 235
Packing Type TUBE
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-DSO-16
Package Name SOIC-16 (002-15547)
Packing Size 235
Packing Type TUBE
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
The S25FS512SDSMFI011 is a 512 Mb (64 MB) NOR flash memory using 65-nm MIRRORBIT™ technology and Eclipse architecture, supporting SPI Multi-I/O with single, dual, quad, and DDR modes up to 80 MB/s. Operating from 1.7 V to 2.0 V, it is AEC-Q100 Grade 1 qualified for -40°C to +125°C. Key features include a 256-/512-byte page buffer, hybrid and uniform sector options, 100,000 program-erase cycles, 20-year data retention, and advanced sector protection.

Features

  • SPI with multi-I/O support
  • DDR and SDR clocking options
  • 24- or 32-bit addressing
  • Compatible with S25FL SPI families
  • Multiple read modes: Normal, Fast, Dual
  • Burst wrap and XIP support
  • 256/512-byte page programming buffer
  • Program and erase suspend/resume
  • Internal ECC with single bit correction
  • Hybrid and uniform sector erase options
  • 100,000 program-erase cycles min
  • 20 year data retention min

Benefits

  • Flexible interface for diverse host
  • High-speed data transfer and boot performance
  • Supports large address spaces for modern
  • Easy migration from legacy SPI designs
  • Optimized for fast and efficient data access
  • Enables execute-in-place (XIP) applications
  • Efficient programming for fast updates
  • Minimized downtime during program/erase
  • Enhanced data reliability and integrity
  • Flexible memory management for varied needs
  • Long device lifetime for demanding use
  • Reliable data storage for mission-critical

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }