Active and preferred
RoHS Compliant
Lead-free

CY14V116N-BZ30XIT

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CY14V116N-BZ30XIT
CY14V116N-BZ30XIT

Product details

  • Density
    16 MBit
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    2.7 V to 3.6 V
  • Organization (X x Y)
    1Mb x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2031
  • Qualification
    Industrial
  • Speed
    30 ns
OPN
CY14V116N-BZ30XIT
Product Status active and preferred
Infineon Package
Package Name FBGA-165 (51-85195)
Packing Size 1000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
Package Name FBGA-165 (51-85195)
Packing Size 1000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
The CY14V116N-BZ30XIT is a 16-Mbit (1024K × 16) nvSRAM that combines fast SRAM with QuantumTrap nonvolatile storage in each cell. It supports hands-off AutoStore on power-down using a small VCAP capacitor, plus hardware or software STORE/RECALL control. Operates from 2.7 V to 3.6 V core and 1.65 V to 1.95 V I/O over -40°C to 85°C in a 165-ball FBGA, with 30 ns access time and 20-year retention.

Features

  • 16-Mbit nvSRAM (1024K × 16)
  • QuantumTrap NVM in each cell
  • AutoStore on power-down via VCAP
  • STORE via HSB pin or software seq
  • RECALL on power-up or software seq
  • Parallel STORE/RECALL of all cells
  • R/W blocked during STORE/RECALL
  • Byte enables BHE/BLE for 8-bit ops
  • VCC core supply 2.7 V to 3.6 V
  • VCCQ I/O supply 1.65 V to 1.95 V
  • 10 µA sleep mode current
  • 20-year data retention

Benefits

  • Retains data through power loss
  • No battery for nonvolatile backup
  • Simple power-down data protection
  • Flexible save/restore control options
  • Fast restart with power-up RECALL
  • Deterministic STORE/RECALL behavior
  • Supports 8-bit or 16-bit bus designs
  • Low sleep current cuts standby power
  • Separate VCC/VCCQ eases level shift
  • High endurance for frequent saves
  • Parallel transfer minimizes downtime
  • Avoids STORE unless SRAM was written

Applications

Documents

Design resources

Developer community

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