Active and preferred
RoHS Compliant
Lead-free

S80KS2564GACHA043

Data Sheet
package

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S80KS2564GACHA043
S80KS2564GACHA043
Data Sheet

Product details

  • Density
    256 MBit
  • Family
    KS-4
  • Interface Frequency (SDR/DDR) (MHz)
    - / 200
  • Interfaces
    HYPERBUS x16
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    1.7 V to 2 V
  • Operating Voltage
    1.8 V
  • Planned to be available until at least
    See roadmap
  • Qualification
    Automotive
Recommended
OPN
S80KS2564GACHA043
Product Status active and preferred
Infineon Package
PG-BGA-49
Package Name FBGA-49 (002-32552)
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-BGA-49
Package Name FBGA-49 (002-32552)
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
The S80KS2564GACHA043 is a 256 Mb HYPERRAM™ self-refresh DRAM (PSRAM) for add-on system memory using a 1.7 V to 2.0 V HYPERBUS™ extended-IO x16 DDR interface with RWDS and RESET#. It supports up to 200 MHz clock, 35 ns max access time, and up to 800 MBps throughput, plus configurable linear or wrapped bursts. Automotive AEC-Q100 Grade 3/2 operation and hybrid sleep/deep power-down modes.

Features

  • HYPERBUS extended-IO interface
  • 16-bit data bus DQ[15:0]
  • DDR transfers on both clock edges
  • 200 MHz max clock rate
  • Up to 800 MBps data throughput
  • 35 ns maximum access time
  • 1.7 V to 2.0 V VCC/VCCQ
  • 1.55 0a 0a standby current (typ.)
  • Hybrid sleep retains data
  • Deep power down stops refresh
  • Partial array refresh (1/8 to 1/2)
  • Active clock stop low-power state

Benefits

  • x16 DDR bus boosts memory bandwidth
  • 35 ns tACC improves responsiveness
  • 1.8 V I/O matches modern SoCs
  • 800 MBps supports high data loads
  • Burst modes optimize host transfers
  • Clock stop cuts stall power use
  • b5A standby reduces idle power
  • Hybrid sleep keeps state at low power
  • Deep power down lowers leakage power
  • Partial refresh reduces standby current
  • RWDS strobe simplifies timing margin
  • RESET# enables reliable recovery

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

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