Active and preferred
RoHS Compliant
Lead-free

S25FS256TDPBHI113

High-Density 256MBit Quad SPI Memory | 52MByte/s Bandwidth, Industrial Grade FS-T Family - Wide Operating Range
Data Sheet
package
ea.
in stock

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

S25FS256TDPBHI113
S25FS256TDPBHI113
ea.
Data Sheet

Product details

  • Density
    256 MBit
  • Family
    FS-T
  • Interface Bandwidth
    52 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    104 / -
  • Interfaces
    Quad SPI
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    1.7 V to 2 V
  • Operating Voltage
    1.8 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2030
  • Qualification
    Industrial
Recommended
OPN
S25FS256TDPBHI113
Product Status active and preferred
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
S25FS256TDPBHI113 is a 256 Mbit NOR Flash (FS-T family) for code and data storage using a Quad SPI interface up to 104 MHz SDR (52 MByte/s). It operates from 1.7 V to 2.0 V over -40°C to 85°C (industrial) and supports 128 KB or 64 KB sectors, 256/512-byte page program, and a 1024-byte OTP Secure Silicon Region. Built-in ECC, SFDP, SafeBoot, and reset options support reliable boot storage.

Features

  • 45-nm MIRRORBIT™ 2-bit-per-cell
  • Uniform 64 KB or 128 KB sectors
  • Configurable sector architecture
  • 256 B or 512 B program buffer
  • SPI 1-1-1 and Quad 1-1-4,1-4-4
  • Up to 104 MHz clock operation
  • ECC on 16-byte data units
  • 1-bit correct, 2-bit detect (ECC)
  • ECC status via EDUS and ECSV regs
  • RD/BY# output for Ready/Busy
  • SafeBoot failure signature in STR1
  • CS# signaling reset + RESET# pin

Benefits

  • 2 bpc lowers cost per stored bit
  • Sector sizes match code vs data
  • Configurable map eases migration
  • Page buffer speeds firmware update
  • Quad I/O enables fast XIP reads
  • 104 MHz supports high throughput
  • ECC improves read data reliability
  • ECC flags speed fault isolation
  • RD/BY# reduces host firmware load
  • SafeBoot enables recovery after fault
  • Reset options improve robustness
  • SFDP support eases host bring-up

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }