Please note that this is an end of life product. Explore the product family for available alternatives. Please note that this is an end of life product. Explore the product family for available alternatives.
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S70KL1282GABHI020
END OF LIFE
discontinued
RoHS Compliant
Lead-free

S70KL1282GABHI020

END OF LIFE
Datasheet
package
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S70KL1282GABHI020
S70KL1282GABHI020
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Datasheet


Product details

  • Density
    128 MBit
  • Family
    KL-2
  • Initial Access Time
    35 ns
  • Interface Bandwidth
    400 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    - / 200
  • Interfaces
    HYPERBUS
  • Lead Ball Finish
    N/A
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    2.7 V to 3.6 V
  • Operating Voltage
    3 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    See roadmap
  • Qualification
    Industrial
  • Technology
    HYPERRAM

OPN
S70KL1282GABHI020
Product Status discontinued
Infineon Package
PG-BGA-24
Package Name BGA-24 (002-15550)
Packing Size 3380
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Country of Assembly (CoA)
TH
Country of Diffusion (CoD)
TW
View product family

Product Status discontinued
Infineon Package
PG-BGA-24
Package Name BGA-24 (002-15550)
Packing Size 3380
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Country of Assembly (CoA)
TH
Country of Diffusion (CoD)
TW
View product family
The S70KL1282GABHI020 is a 128 Mb HYPERRAM™ self-refresh DRAM (PSRAM) with a HYPERBUS™ interface and 3.0 V supply (2.7 V to 3.60 V). It supports DDR transfers with up to 200 MHz clock, up to 400 MBps bandwidth, and 35 ns maximum access time. In a 24-ball FBGA, it offers interface standby, hybrid sleep, and deep power down, with standby current specified to 750 µA at 3.6 V, 105°C.

Features

  • HYPERBUS interface
  • 1.7 V to 2.0 V VCC option
  • 2.7 V to 3.60 V VCC option
  • 8-bit DDR data bus (DQ[7:0])
  • 200 MHz maximum clock rate
  • Up to 400 MBps throughput
  • 35 ns maximum access time (tACC)
  • Wrapped bursts 16/32/64/128 B
  • RWDS strobe and write data mask
  • DCARS option shifts RWDS phase
  • Hybrid sleep retains data
  • Deep power down stops refresh

Benefits

  • High bandwidth with few pins
  • Fits 1.8 V or 3.0 V logic rails
  • DDR bus reduces system pin count
  • 200 MHz supports fast processors
  • 400 MBps feeds high-rate buffers
  • 35 ns tACC reduces read latency
  • Burst sizes match cache-line needs
  • RWDS eases DDR timing closure
  • DCARS improves read eye margin
  • Hybrid sleep cuts power, keeps data
  • DPD minimizes leakage when off
  • Clock-stop lowers stall current

Applications

Documents

Design resources

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Developer community