AURIX™ TriCore™ MCUs

Infineon AURIX™ TriCore™ MCU: 32-bit real-time automotive microcontroller with built-in functional safety for demanding automotive and industrial use

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What is the Infineon AURIX™ TriCore™ MCU family?

The AURIX™ TriCore™ family combines a reduced instruction set computing (RISC) load-store core, a digital signal processor (DSP), and microcontroller input/output logic in one re-programmable core. Infineon organizes the portfolio into three generations — TC2x, TC3x, and TC4x — differentiated primarily by manufacturing process node and performance tier: TC3x is built on 40 nm embedded flash technology, while TC4x moves to 28 nm for higher compute density at a comparable power budget.

What unifies the family across generations is a scalable multi-core architecture, embedded functional safety compliant with ISO 26262 up to Automotive Safety Integrity Level D (ASIL D), and software and toolchain compatibility that lets a design migrate between generations without a full rewrite. Each generation adds cores, memory, and interfaces, but the TriCore™ instruction set architecture (ISA) and the AUTOSAR-based software stack carry forward.

AURIX™ MCUs are deployed primarily in automotive systems — powertrain, chassis, braking, electric power steering, airbags, connectivity, and ADAS — and in industrial applications such as multi-axis motor control and real-time signal processing. The sections below detail the ISA parameters that drive part selection, how the three generations differ in performance, and how to select the right device for a given design.

Learn more about AURIX™ TC2x family now
Learn more about AURIX™ TC3x family now
Learn more about AURIX™ TC4x family now

Which TriCore™ ISA parameters matter most for real-time design?

TriCore™'s ISA unifies three design disciplines in a single core: the real-time response of a microcontroller, the computational throughput of a DSP, and the code density of a RISC load-store architecture. It supports both 16-bit and 32-bit instruction formats, letting designers trade code size against execution speed within the same core.

  • Memory and addressing:

TriCore™ addresses up to 4 GB of memory space, which supports the larger code bases typical of ADAS and body-control applications without external memory banking. Byte- and bit-level addressing, together with built-in memory protection, let a single device isolate safety-critical and non-safety tasks.

  • Instruction efficiency:

Mixed 16-/32-bit instruction encoding reduces code memory footprint without sacrificing computational density, and branch prediction combined with zero-overhead loop support reduces cycle overhead in tight control loops — a direct benefit for closed-loop control tasks such as motor commutation.

  • Processing power:

Each core integrates dual, single-clock-cycle 16x16-bit multiply-accumulate (MAC) units, with an optional floating-point unit (FPU) and memory management unit (MMU) available depending on device variant. Single Instruction Multiple Data (SIMD) support processes two 16-bit or four 8-bit operands per instruction, which speeds up sensor-signal filtering and similar DSP-style workloads.

  • Interrupt and control:

A flexible interrupt-prioritization scheme with fast, automatic context switching keeps interrupt latency low — a requirement for real-time automotive control loops such as engine timing or anti-lock braking, where a missed deadline is a functional-safety event, not just a performance regression.

How do TC2x, TC3x, and TC4x differ in performance and process?

TriCore™ technology traces back to Infineon's 1999 AUDO (Automotive Unified Processor) family, from which the AURIX™ line evolved in 2012. Since then, the architecture has advanced through three AURIX™ generations, each defined by a process-node and performance step rather than by a single feature.

AURIX™ TC3x is built on 40 nm embedded flash technology and scales up to six TriCore™ 1.62 cores at a full clock frequency of 300 MHz, with up to 16 MB of flash and more than 6 MB of integrated RAM. AURIX™ TC4x advances to 28 nm manufacturing and the TriCore™ v1.8 core, reaching up to six cores at 500 MHz in lockstep, with 24 MB of on-chip non-volatile memory (NVM). Both generations use Infineon's dual frontend manufacturing strategy, which runs two independent production sites to maintain continuous global supply.

Generation comparison

  • AURIX™ TC2x:
    • Maximum core clock: 300 MHz
    • Maximum on-chip memory: 8 MB flash / 2.7 MB RAM
  • AURIX™ TC3x:
    • Process node: 40 nm embedded flash
    • Maximum cores: 6 TriCore™ v1.6.2 cores
    • Maximum core clock: 300 MHz
    • Maximum on-chip memory: 16 MB flash / >6 MB RAM
  • AURIX™ TC4x:
    • Process node: 28 nm
    • Maximum cores: 6 TriCore™ v1.8 cores
    • Maximum core clock: 500 MHz
    • Maximum on-chip memory: 24 MB on-chip NVM

AUTOSAR (Automotive Open System Architecture) libraries and safety software are available for both generations, helping engineers meet their system's target Automotive Safety Integrity Level (ASIL). As a selection starting point: TC3x suits designs that need proven 40 nm-node reliability in powertrain or body applications; TC4x suits compute-intensive designs such as ADAS domain controllers or zonal E/E architectures that need the additional headroom of the 28 nm node.

What evaluation tools and resources are available for AURIX™?

Infineon provides AURIX™-specific kits, technical documentation, software development tools, and training to accelerate design-in.

Kits & Samples

AURIX™ Lite Kits are affordable, beginner-friendly development boards designed for rapid prototyping and evaluation. These kits allow developers to test and implement AURIX™ solutions quickly.

Documentation and software

Technical documentation — including datasheets, user manuals, and application notes — is published through Infineon's AURIX™ digital collaterals portal in HTML format, viewable across devices without a separate download. AURIX™ Development Studio provides the development environment itself: an Eclipse-based IDE, C compiler, multi-core debugger, and the Infineon Low-Level Driver (iLLD) library, with no time or code-size limitation. For software integration, the MC-ISAR AUTOSAR Microcontroller Abstraction Layer (MCAL) and SafeTlib safety-test library support ISO 26262-compliant application development, and AURIX™ DRIVECORE bundles this software to simplify migration between devices.

Learn more about AURIX™ Kits & Samples
Discover AURIX™ digital collaterals

Register on the myInfineon Collaboration Platform (myICP) for access to restricted technical documentation, training materials, and add-on tools.

myICP
How to register

Microcontroller Training and Video Hub provides tutorials and hands-on guides for AURIX™ Development Studio, suited to both first-time and experienced AURIX™ users.

Microcontroller Training and Video Hub

AURIX™ Preferred Design Houses (PDH): specialist design support

Infineon supports AURIX™ TriCore™ MCU designs through a structured, two-tier technical support model: local field application engineers (FAEs) handle initial design guidance, and dedicated automotive security experts handle complex safety and security questions. Dedicated on-site consulting can be arranged for designs that need it.

The AURIX™ Preferred Design Houses (PDH) program extends this support globally through an Infineon-trained partner network, rather than a generic reseller channel. PDH partners provide hardware and software design services for AURIX™-based systems, including AUTOSAR MCAL configuration, SafeTlib safety-software integration, and reference-design development.

AURIX™ Preferred Design Houses (PDH)

Which AURIX™ software components meet ISO 26262 ASIL-D?

Infineon's AURIX™ embedded software portfolio is qualified to ISO 26262:2018 up to Automotive Safety Integrity Level D (ASIL D) and ISO 21434 automotive cybersecurity, and developed to Automotive SPICE (ASPICE — Automotive Software Process Improvement and Capability dEtermination) up to Level 3. ISO 21434 addresses automotive cybersecurity engineering requirements, complementing the functional-safety scope of ISO 26262.

The portfolio covers the full AURIX™ MCU family -- TC2x, TC3x, and TC4x -- and includes:

  • MC-ISAR AUTOSAR MCAL — Infineon's AUTOSAR-compliant Microcontroller Abstraction Layer (MCAL) product, for rapid application development against a verified driver base.
  • SafeTlib — a safety software library of self-test routines, including software-based self-test (SBST) for the CPU core and internal/external watchdog handling.
  • CDSP library — the Converter Digital Signal Processor (CDSP) library, for efficient signal post-processing.

High-performance data-routing software — reduces CPU load during high-speed data transfer between peripherals and memory.

This common software base helps developers build scalable, future-proof systems across all three AURIX™ generations without re-qualifying the safety case for each device.

AURIX™ Embedded Software

Which systems use AURIX™ TriCore™ MCUs in real applications?

AURIX™ sub-family selection generally follows system topology rather than end-market label alone:

  • Electric power steering (EPS) — TC3x or TC4x is well suited to the ASIL D functional-safety margin an EPS control loop typically requires, with deterministic interrupt latency for torque-sensor feedback.
  • 48V mild-hybrid DC-DC conversion and battery management — TC3x's hexa-core architecture and on-chip ADCs are suited to the control-loop and monitoring demands of electrified powertrains.
  • Radar front-end and sensor-fusion processing — TC4x's Signal Processing Unit (SPU) accelerator is designed for radar signal processing within an ADAS domain controller.
  • Zonal and domain-control E/E architectures — TC4x's 5 Gbps Ethernet and PCIe connectivity support the higher data bandwidth these architectures typically require between zones.
  • Airbag and restraint systems — TC2x or TC3x can provide the ASIL D safety margin and lockstep core redundancy these fail-safe systems typically need.
  • Multi-axis industrial motor control — the on-chip DSP capability can support real-time commutation and signal processing without an external signal processor.

TC2x, TC3x, or TC4x: AURIX™ MCU selection decision guide

Three factors drive the choice between AURIX™ generations: compute performance headroom, process-node maturity preference, and target ASIL safety level.

  • If your application needs proven 40 nm-node reliability in a harsh automotive environment (for example, an engine-bay-mounted ECU) — evaluate TC3x.
  • If your design needs higher compute density at 28 nm for ADAS, domain control, or zonal architectures — evaluate TC4x.
  • If your system safety goal requires ISO 26262 ASIL D compliance — all three generations provide hardware safety mechanisms toward ASIL D; verify the specific certification level against your safety case, since ASIL support varies by device variant within a generation.

All AURIX™ generations share backward-compatible software and toolchain support, which lets a design migrate between TC2x, TC3x, and TC4x without a full redesign.

Generation selection summary

  • TC2x:
    • Maximum core clock: 300 MHz
    • Maximum on-chip memory: 8 MB flash
    • Fits best when: Cost-sensitive ASIL D designs on a mature, established node
  • TC3x:
    • Maximum core clock: 300 MHz (6 cores)
    • Maximum on-chip memory: 16 MB flash
    • Fits best when: Domain control/sensor fusion needing hexa-core headroom at 40 nm
  • TC4x:
    • Maximum core clock: 500 MHz (6 cores)
    • Maximum on-chip memory: 24 MB on-chip NVM
    • Fits best when: AI-accelerated ADAS, zonal E/E, or designs needing PCIe / 5 Gbps Ethernet

What is the Infineon AURIX™ TriCore™ MCU family?

The AURIX™ TriCore™ family combines a reduced instruction set computing (RISC) load-store core, a digital signal processor (DSP), and microcontroller input/output logic in one re-programmable core. Infineon organizes the portfolio into three generations — TC2x, TC3x, and TC4x — differentiated primarily by manufacturing process node and performance tier: TC3x is built on 40 nm embedded flash technology, while TC4x moves to 28 nm for higher compute density at a comparable power budget.

What unifies the family across generations is a scalable multi-core architecture, embedded functional safety compliant with ISO 26262 up to Automotive Safety Integrity Level D (ASIL D), and software and toolchain compatibility that lets a design migrate between generations without a full rewrite. Each generation adds cores, memory, and interfaces, but the TriCore™ instruction set architecture (ISA) and the AUTOSAR-based software stack carry forward.

AURIX™ MCUs are deployed primarily in automotive systems — powertrain, chassis, braking, electric power steering, airbags, connectivity, and ADAS — and in industrial applications such as multi-axis motor control and real-time signal processing. The sections below detail the ISA parameters that drive part selection, how the three generations differ in performance, and how to select the right device for a given design.

Learn more about AURIX™ TC2x family now
Learn more about AURIX™ TC3x family now
Learn more about AURIX™ TC4x family now

Which TriCore™ ISA parameters matter most for real-time design?

TriCore™'s ISA unifies three design disciplines in a single core: the real-time response of a microcontroller, the computational throughput of a DSP, and the code density of a RISC load-store architecture. It supports both 16-bit and 32-bit instruction formats, letting designers trade code size against execution speed within the same core.

  • Memory and addressing:

TriCore™ addresses up to 4 GB of memory space, which supports the larger code bases typical of ADAS and body-control applications without external memory banking. Byte- and bit-level addressing, together with built-in memory protection, let a single device isolate safety-critical and non-safety tasks.

  • Instruction efficiency:

Mixed 16-/32-bit instruction encoding reduces code memory footprint without sacrificing computational density, and branch prediction combined with zero-overhead loop support reduces cycle overhead in tight control loops — a direct benefit for closed-loop control tasks such as motor commutation.

  • Processing power:

Each core integrates dual, single-clock-cycle 16x16-bit multiply-accumulate (MAC) units, with an optional floating-point unit (FPU) and memory management unit (MMU) available depending on device variant. Single Instruction Multiple Data (SIMD) support processes two 16-bit or four 8-bit operands per instruction, which speeds up sensor-signal filtering and similar DSP-style workloads.

  • Interrupt and control:

A flexible interrupt-prioritization scheme with fast, automatic context switching keeps interrupt latency low — a requirement for real-time automotive control loops such as engine timing or anti-lock braking, where a missed deadline is a functional-safety event, not just a performance regression.

How do TC2x, TC3x, and TC4x differ in performance and process?

TriCore™ technology traces back to Infineon's 1999 AUDO (Automotive Unified Processor) family, from which the AURIX™ line evolved in 2012. Since then, the architecture has advanced through three AURIX™ generations, each defined by a process-node and performance step rather than by a single feature.

AURIX™ TC3x is built on 40 nm embedded flash technology and scales up to six TriCore™ 1.62 cores at a full clock frequency of 300 MHz, with up to 16 MB of flash and more than 6 MB of integrated RAM. AURIX™ TC4x advances to 28 nm manufacturing and the TriCore™ v1.8 core, reaching up to six cores at 500 MHz in lockstep, with 24 MB of on-chip non-volatile memory (NVM). Both generations use Infineon's dual frontend manufacturing strategy, which runs two independent production sites to maintain continuous global supply.

Generation comparison

  • AURIX™ TC2x:
    • Maximum core clock: 300 MHz
    • Maximum on-chip memory: 8 MB flash / 2.7 MB RAM
  • AURIX™ TC3x:
    • Process node: 40 nm embedded flash
    • Maximum cores: 6 TriCore™ v1.6.2 cores
    • Maximum core clock: 300 MHz
    • Maximum on-chip memory: 16 MB flash / >6 MB RAM
  • AURIX™ TC4x:
    • Process node: 28 nm
    • Maximum cores: 6 TriCore™ v1.8 cores
    • Maximum core clock: 500 MHz
    • Maximum on-chip memory: 24 MB on-chip NVM

AUTOSAR (Automotive Open System Architecture) libraries and safety software are available for both generations, helping engineers meet their system's target Automotive Safety Integrity Level (ASIL). As a selection starting point: TC3x suits designs that need proven 40 nm-node reliability in powertrain or body applications; TC4x suits compute-intensive designs such as ADAS domain controllers or zonal E/E architectures that need the additional headroom of the 28 nm node.

What evaluation tools and resources are available for AURIX™?

Infineon provides AURIX™-specific kits, technical documentation, software development tools, and training to accelerate design-in.

Kits & Samples

AURIX™ Lite Kits are affordable, beginner-friendly development boards designed for rapid prototyping and evaluation. These kits allow developers to test and implement AURIX™ solutions quickly.

Documentation and software

Technical documentation — including datasheets, user manuals, and application notes — is published through Infineon's AURIX™ digital collaterals portal in HTML format, viewable across devices without a separate download. AURIX™ Development Studio provides the development environment itself: an Eclipse-based IDE, C compiler, multi-core debugger, and the Infineon Low-Level Driver (iLLD) library, with no time or code-size limitation. For software integration, the MC-ISAR AUTOSAR Microcontroller Abstraction Layer (MCAL) and SafeTlib safety-test library support ISO 26262-compliant application development, and AURIX™ DRIVECORE bundles this software to simplify migration between devices.

Learn more about AURIX™ Kits & Samples
Discover AURIX™ digital collaterals

Register on the myInfineon Collaboration Platform (myICP) for access to restricted technical documentation, training materials, and add-on tools.

myICP
How to register

Microcontroller Training and Video Hub provides tutorials and hands-on guides for AURIX™ Development Studio, suited to both first-time and experienced AURIX™ users.

Microcontroller Training and Video Hub

AURIX™ Preferred Design Houses (PDH): specialist design support

Infineon supports AURIX™ TriCore™ MCU designs through a structured, two-tier technical support model: local field application engineers (FAEs) handle initial design guidance, and dedicated automotive security experts handle complex safety and security questions. Dedicated on-site consulting can be arranged for designs that need it.

The AURIX™ Preferred Design Houses (PDH) program extends this support globally through an Infineon-trained partner network, rather than a generic reseller channel. PDH partners provide hardware and software design services for AURIX™-based systems, including AUTOSAR MCAL configuration, SafeTlib safety-software integration, and reference-design development.

AURIX™ Preferred Design Houses (PDH)

Which AURIX™ software components meet ISO 26262 ASIL-D?

Infineon's AURIX™ embedded software portfolio is qualified to ISO 26262:2018 up to Automotive Safety Integrity Level D (ASIL D) and ISO 21434 automotive cybersecurity, and developed to Automotive SPICE (ASPICE — Automotive Software Process Improvement and Capability dEtermination) up to Level 3. ISO 21434 addresses automotive cybersecurity engineering requirements, complementing the functional-safety scope of ISO 26262.

The portfolio covers the full AURIX™ MCU family -- TC2x, TC3x, and TC4x -- and includes:

  • MC-ISAR AUTOSAR MCAL — Infineon's AUTOSAR-compliant Microcontroller Abstraction Layer (MCAL) product, for rapid application development against a verified driver base.
  • SafeTlib — a safety software library of self-test routines, including software-based self-test (SBST) for the CPU core and internal/external watchdog handling.
  • CDSP library — the Converter Digital Signal Processor (CDSP) library, for efficient signal post-processing.

High-performance data-routing software — reduces CPU load during high-speed data transfer between peripherals and memory.

This common software base helps developers build scalable, future-proof systems across all three AURIX™ generations without re-qualifying the safety case for each device.

AURIX™ Embedded Software

Which systems use AURIX™ TriCore™ MCUs in real applications?

AURIX™ sub-family selection generally follows system topology rather than end-market label alone:

  • Electric power steering (EPS) — TC3x or TC4x is well suited to the ASIL D functional-safety margin an EPS control loop typically requires, with deterministic interrupt latency for torque-sensor feedback.
  • 48V mild-hybrid DC-DC conversion and battery management — TC3x's hexa-core architecture and on-chip ADCs are suited to the control-loop and monitoring demands of electrified powertrains.
  • Radar front-end and sensor-fusion processing — TC4x's Signal Processing Unit (SPU) accelerator is designed for radar signal processing within an ADAS domain controller.
  • Zonal and domain-control E/E architectures — TC4x's 5 Gbps Ethernet and PCIe connectivity support the higher data bandwidth these architectures typically require between zones.
  • Airbag and restraint systems — TC2x or TC3x can provide the ASIL D safety margin and lockstep core redundancy these fail-safe systems typically need.
  • Multi-axis industrial motor control — the on-chip DSP capability can support real-time commutation and signal processing without an external signal processor.

TC2x, TC3x, or TC4x: AURIX™ MCU selection decision guide

Three factors drive the choice between AURIX™ generations: compute performance headroom, process-node maturity preference, and target ASIL safety level.

  • If your application needs proven 40 nm-node reliability in a harsh automotive environment (for example, an engine-bay-mounted ECU) — evaluate TC3x.
  • If your design needs higher compute density at 28 nm for ADAS, domain control, or zonal architectures — evaluate TC4x.
  • If your system safety goal requires ISO 26262 ASIL D compliance — all three generations provide hardware safety mechanisms toward ASIL D; verify the specific certification level against your safety case, since ASIL support varies by device variant within a generation.

All AURIX™ generations share backward-compatible software and toolchain support, which lets a design migrate between TC2x, TC3x, and TC4x without a full redesign.

Generation selection summary

  • TC2x:
    • Maximum core clock: 300 MHz
    • Maximum on-chip memory: 8 MB flash
    • Fits best when: Cost-sensitive ASIL D designs on a mature, established node
  • TC3x:
    • Maximum core clock: 300 MHz (6 cores)
    • Maximum on-chip memory: 16 MB flash
    • Fits best when: Domain control/sensor fusion needing hexa-core headroom at 40 nm
  • TC4x:
    • Maximum core clock: 500 MHz (6 cores)
    • Maximum on-chip memory: 24 MB on-chip NVM
    • Fits best when: AI-accelerated ADAS, zonal E/E, or designs needing PCIe / 5 Gbps Ethernet
Documents

AURIX™ TriCore™ MCUs