Optimized AURIX™ - XILINX FPGA Link
Xylon HSSL IP Core

Flexible safety performance extension : Optimized AURIX™ - XILINX FPGA Link

Xylon HSSL IP Core

Infineon Technologies AG, Xilinx, Inc. and Xylon, d.o.o. cooperate for more flexibility in using safety microcontrollers in automotive and industrial applications. The new IP-Core of Xylon enables high-speed communication between microcontrollers of Infineon's AURIX family (TC2xx and TC3xx)  and Xilinx SoC (System-on-Chip), MPSoC (MultiProcessor SoC) and FPGA (Field Programmable Gate Arrays) devices via the Infineon High Speed Serial Link (HSSL). This serial link supports baudrates of up to 320 Mbaud at a net payload data-rate of up to 84%.

The new IP core will allow system developers to combine functional safety and security provided by AURIX™ with the wide range of functional possibilities brought to the table by the Xilinx devices. Linked devices can access and control each other’s internal and connected resources through the HSSL .

Xylon HSSL IP Core Features

  • Currently supports Xilinx 7 Series and Zynq-7000 SoC device families
  • Support for Xilinx UltraScale, UltraScale+ FPGA devices, and Zynq UltraScale+ MPSoC planned for the near future.
  • HSSL slave device
  • Up to 320 Mbaud/s baud rate
  • ARM AMBA AXI4-Lite bus protocol compliant as a slave device
  • ARM AMBA AXI4 bus protocol compliant as a master device

3.25 GB of addresable space covers accesses to:

  • FPGA fabric registers and RAM
  • PS section register space and OCM
  • On-board linearly addresable FLASH devices
  • On-board DDR memory

For development support, the partners offer a starter kit

The Infineon Aurix evaluation kit on the left. On the right, Xilinx Zynq-7000 SoC based ZC706 Evaluation Kit with the manuallymodified Xylon FMC board.

 kit content :

Zynq-7000 SoC Demo Design Example –  Block Diagram

 

  • The HSSL IP core (HSSL #0) can access register sets of all SoC IP cores through the PS 7 AXI Interconnect
  • The HSSL control module can access internal HSCT, HSSL and BCU register space through the same AXI infrastructure
  • HSSL IP core can access PS register space and on-board memory through GP and HP AXI3 ports on PL-PS interface
  • Programmable logiCLK IP core changes clocking on the fly and enables HSSL IP core setup to the required baud rate

 

  

Availability


The new IP Core and development kit will be available in March 2019 via the XCL logicBRICKS IP cores library

Demo boards will be shown at embedded world 2019 :                                                                                                          

  • Infineon (booth #231, hall 3a)  
  • distribution partner EBV (booth #229, hall 3A)

 Click here to learn more about the IP core

Xylon technical support 

support@logicbricks.com  

 Infineon technical support

  1. Please register under myinfineon.com (hyperlink) with your company e-mail address
  2. Send login name to: AURIX@infineon.com
  3. Automated update service will be provided for new documents once you are registered
  4. Full registration process can take up to 24h to be completed (due to different time zones).

Click here to see the step-by-step instructions to get registered.