Active and preferred
RoHS Compliant
Lead-free

S80KS2564GACHI040

256MBit 1.8 V Industrial (85°C) HyperBus x16 HYPERRAM Gen 3.0 in 49 FBGA
Data Sheet
package
ea.
in stock

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S80KS2564GACHI040
S80KS2564GACHI040
ea.
Data Sheet

Product details

  • Density
    256 MBit
  • Family
    KS-4
  • Interface Frequency (SDR/DDR) (MHz)
    - / 200
  • Interfaces
    HYPERBUS x16
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    1.7 V to 2 V
  • Operating Voltage
    1.8 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    See roadmap
  • Qualification
    Industrial
  • Technology
    HYPERRAM
Recommended
OPN
S80KS2564GACHI040
Product Status active and preferred
Infineon Package
PG-BGA-49
Package Name FBGA-49 (002-32552)
Packing Size 260
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-BGA-49
Package Name FBGA-49 (002-32552)
Packing Size 260
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
The S80KS2564GACHI040 is a 256 Mb HYPERRAM self-refresh DRAM (PSRAM) with a 1.8 V (1.7 V to 2.0 V) HYPERBUS extended-IO x16 interface. It supports up to 200 MHz DDR operation for up to 800 MBps throughput and 35 ns max access time. In a 49-ball FBGA, the industrial grade (-40b0C to 85b0C) device includes partial-array refresh, hybrid sleep, and deep power-down modes for low standby power.

Features

  • HYPERBUS extended-IO x16 bus
  • DDR transfers both clock edges
  • 200 MHz maximum clock rate
  • Up to 800 MBps data throughput
  • Maximum access time tACC 35 ns
  • Optional differential clock CK/CK#
  • RWDS strobe and write data mask
  • Configurable linear or wrapped burst
  • 1.7 V to 2.0 V VCC/VCCQ supply
  • Hybrid sleep retains memory data
  • Deep power down stops refresh
  • ESD: 2 kV HBM, 500 V CDM

Benefits

  • x16 DDR boosts bandwidth per pin
  • 800 MBps enables fast frame buffer
  • 35 ns tACC cuts read latency
  • Diff clock improves noise margin
  • RWDS eases timing and data mask
  • Burst modes optimize host traffic
  • 1.8 V supply fits modern MCUs
  • Hybrid sleep saves power, keeps data
  • DPD minimizes energy when unused
  • ESD ratings improve handling yield
  • Overshoot spec eases SI margins
  • Active clock stop reduces ICC level

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

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