PSRAM – Pseudostatic RAM
HYPERRAM™ - Low pin-count, High bandwidth pSRAM in small footprint
HYPERRAM™ is high-speed CMOS, self-refresh DRAM, with HyperBus™ interface. It’s memory array is internally structured like DRAM, but externally act like SRAM.
The DRAM array requires periodic refresh to maintain data integrity. HyperRAM™ internally manages the refresh operations on the DRAM array when the memory is not being actively read or written by master (host). Since the host is not required to manage any refresh operations, the DRAM array appears to the host as static cells that retain data without refresh. Hence, HYPERRAM™ is described as Pseudo Static RAM (PSRAM)
These low-power, high performance and low pin-count pSRAMs, are suitable for applications requiring additional RAM for buffering data, audio, images, video or as a scratchpad for math and data-intensive operations.
Density : 64Mb, 128Mb, 256Mb, 512Mb
Interface: HyperBus™(x8), Octal xSPI(x8) and HyperBus™ Extended I/O (x16)
HYPERRAM™ 2.0 is the second generation of Low pin-count pSRAM from Infineon that support throughputs of up to 400MBps. HYPERRAM™ 2.0 products are available from 64Mb to 512Mb. Our third-generation pSRAM product - HYPERRAM™ 3.0, doubles the throughput to 800MBps using a new 16-bit extended version of the HyperBus™ interface. 256Mb HYPERRAM™ 3.0 products are now available in production.
These pSRAM products supports JEDEC compliant Octal extended SPI interface (Octal xSPI) and HyperBus™ interface.
Key Features
- Small Form Factor - FBGA package to ensure small PCB footprint
- Low Pin-Count - Low pin-count to aid design simplicity and reduce system cost
- Low Power - Hybrid sleep mode and partial array refresh for energy efficiency
- High Throughput - High read/write bandwidth to maximize system performance
HyperBus™ is a low signal count, DDR interface, that achieves high-speed read and write throughput. It utilizes a high-speed 8-bit DDR interface for both address and data along with a differential clock, a read/write latch signal, and a chip select.
HyperBus™ can also support external NOR flash and RAM on the same bus, and works with any microcontroller with a HyperBus™ compatible peripheral interface. This only require 13-pins for data transactions (12-pin HyperBus™ + 1 additional chip select for the second memory device).
To understand how the HyperRAM™ enables a low-pin expansion memory solution, read this whitepaper.
HYPERRAM™ products achieve far higher throughput per pin compared to competing technologies such as traditional pSRAMs and SDR DRAMs which are based on a parallel interface. The in-built self-refresh circuitry and low-power features such as partial array refresh and hybrid sleep enable lower power consumption making HyperRAM apt for power constrained applications such as wearables and IoT devices.
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- Watch the Introduction to HYPERRAM™ 2.0 video
- Get and overview of the product features
- Understand the product applications
- Download the datasheets
- Read the applications notes
- Use the Product Selector to select the appropriate product
- Get your schematics reviewed by the Infineon Applications Engineering Team using Infineon Developer Community
HYPERRAM’s high throughput, low pin-count, smaller footprint and energy efficiency makes it as an ideal expansion memory choice for a variety of automotive, industrial and communication applications.
Automotive Instrument Cluster
- Automotive MCU's have limited internal video RAM
- Require low pin-count, low complexity interface
- Require fast bus speeds for smooth graphics rendering
- Require high-reliability and automotive qualification
For more info regarding Automotive instrument cluster Read here
Industrial Machine Vision camera
- FPGA have limited internal RAM resources
- Require optimized external memory interface IP
- Require low pin-count solution to reduce complexity
For more info regarding Industrial applications Read here
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