Infineon Technical Presentations at ISSCC 2004: Papers Highlight Innovation Leadership in DNA Sensory-Arrays, Low-Cost RFID Tags, ADC Chip Design and High-Speed Communications
At this years conference researchers from Infineon are presenting seven papers across a wide range of topics. One paper will present significant enhancements to the companys electronic DNA sensor chip technology. A new circuit, system and packaging concept for RFID technology, showing a path toward the one cent chip needed to replace visual bar codes, is described. Another presentation will describe the first working analog circuit produced in 90 nm technology, an innovative design of a high-speed A/D converter with very low power consumption. And four separate papers will describe new CMOS-based circuits for wireline and wireless communications, including a low-power four channel ADSL2+ Analog Front End, a power-optimized delta-sigma modulator for ADSL, a fully integrated 13GHz PLL, and a high performance 10-bit ADC with new algorithms for Wireless LAN.
The titles and short summaries of each paper are listed here:
New Electronic DNA Sensor Chip: Building on its earlier breakthrough work in developing a fully electronic DNA sensor array with 128 sensor positions, Infineon will present an enhanced chip design with fully integrated, on-chip analog-to-digital (ADC) conversion for each sensor pixel. The demonstrated 16x8 CMOS sensor array can measure very low currents produced by the presence of target molecules, providing a robust platform for a wide range of potential applications in biotechnology and pharmacological research.
Paper 788 A Fully Electronic DNA Sensor with 128 Positions and In-Pixel A/D Conversion
Infineon is developing a fully electronic approach to DNA sample detection to create the basis for diagnostics systems that are easier to use and less costly than current commercially available optical-based systems. The 128 sensor pixels in this design consist of a circuit that controls the sensor electrode voltages and provides amplified copies of the sensor currents at the pixel output. Advantages of integrating the ADC circuits include an increase in homogeneity of the sensor circuit response, digital data sampling inside the pixel, increased robustness and parallel concurrent readout of all sensors.
Ultra Low-Cost RFID Solution: Manufacturers and sellers of retail products are leading efforts to replace bar codes with RFID (Radio Frequency Identification) solutions, providing an electronic data method that ultimately will improve consumer service. Reducing the costs of RFID tags is a critical step to increasing the number and volume of applications for the technology.
Paper 1068 Towards the One-Cent RFID Tags: AC-only Driven Circuits and Side-Wall Contact Packaging
Infineon describes a new approach to RFID chip design using circuits that are directly AC-powered. This eliminates the need for area-consuming circuit blocks for AC/DC conversion, including rectifiers, buffer capacitances, clock generator and power-up circuits. Infineon developed logic elements based on this concept and will demonstrate a working system based on the new kind of circuits. For a 96-bit memory design, meeting industry specifications for an Electronic Product Code (EPC), the AC-only approach enables a system design consuming silicon area of less than 0.1 mm 2 when manufactured using a 0.13µm CMOS process. Infineon also describes a new packaging technology that uses a sidewall contact to facilitate the assembling process. Using the new AC-powered circuits, a simple coding scheme and the sidewall contact packaging, an RFID tag at a cost of about One Cent appears feasible.
90nm Chip Innovation: Low power and high performance Analog/Digital (A/D) conversion is the key in many applications, especially in portable systems. In this paper Infineon shows that a parallel layout of simple ADC structures achieves not only higher speeds but also new levels of power efficiency. In this design, eight successive approximation ADCs are put in parallel to get a high throughput at extremely very low power.
Paper 935 A 6b 500MHz 10mW ADC Array in Digital 90nm CMOS
The presented A/D converter is the first working analog circuit based on 90nm CMOS technology. The Infineon researchers achieved a sampling rate of 600MHz at a power consumption of only 10mW. The Figure-of-Merit (FoM) of this innovative ADC design calculated on power dissipation, effective number of bits and input frequency shows the best value of all recently presented ISSCC publications.
High-Speed Communications Circuits: Four Papers In this paper Infineon presents an Analog Front End (AFE) that supports the ADSL2+ standard. ADSL2+ is an enhancement of the proven ADSL wireline communications standard. It operates at a downstream frequency range of 2.2MHz and as an option at an extended frequency range up to more then 4MHz, which enables increased data rates for shorter loops or longer overall range and will allow for new applications.
Paper 996 A Four Channel ADSL2+ Analog Front End for CO Applications with 75mW per Channel Built in 0.13µm CMOS
The Infineon AFE design is based on 0.13µm CMOS technology and optimized in performance, power consumption and chip area. The AFE contains four channels, each integrating all analog and digital codec blocks, filters, 14bit A/D and D/A converters. The power consumption of 75mW per channel is about two times lower compared to other ADSL AFEs ever reported. Linearity is measured with more than 80dBc in all operating modes ending up in very competitive MTPR values of 75dBc in the transmit channel.
Paper 998 A Power-Optimized Switched-Capacitor 14-Bit Delta-Sigma Modulator for ADSL CO Applications in 0.13µm CMOS with 1.5V SupplyDigital Subscriber Line (DSL) applications require high resolution and wide bandwidth A/D converters. On the other hand the dissipated power is one important limiting factor for high integration ADSL linecard designs apart from any crosstalk problems.
In this paper Infineon researchers will describe a Switched-Capacitor Multibit Delta-Sigma ADC including a reference voltage buffer implemented in 0.13µm CMOS. The single loop 3-bit modulator features a 14-bit and 13-bit dynamic range over a 276kHz and 1.5MHz signal bandwidth respectively. The achieved power efficiency of the presented SC converter, just 8mW dissipation from 1.5 V supply clocked at 105MHz , is the best figure reported in the literature so far. The robust and low cost ADC design is targeted for high volume production.
Paper 738 A Fully Integrated 13GHz Delta-Sigma Fractional-N PLL in 0.13µm CMOSThe circuit design presented by Infineon is the first fully integrated CMOS PLL reaching 13GHz. This 13GHz PLL aims for future high-speed WLAN systems in the 17GHz ISM band. The highly integrated chip includes all related functionality like a differentially tuned LC-VCO, IQ-divider, low power prescaler, differential phase frequency detector, charge pump, loop filter and a noise shaping modulator. The total power consumption is 60mW from a 1.5V supply. With this work, Infineon researchers prove the feasibility of frequency synthesis in the >10GHz range, targeting fully integrated CMOS System-on-Chip solutions for future WLAN systems.
Paper 1046 An 80MHz, 10-Bit Pipeline ADC with Dynamic Range Doubling and Dynamic Reference Selection Algorithm for Wireless LANBaseband processors for the new Wireless LAN (802.11 x) standards demand high performance CMOS A/D converters. For portable and low cost applications, pure digital CMOS with low power consumption and small chip areas are a must. In this paper a 10-bit 80MHz pipeline ADC that consumes only 22mA at 1.5V will be described. The power consumption is reduced by a factor of two compared to previous published designs. The complete design occupies only 0,3mm 2 die area in 0.13µm CMOS technology. The performance leap has been achieved based on a conventional 1.5-bit pipeline architecture using two new algorithms: dynamic range-doubling (DRD), and dynamic reference selection (DRS).