Infineon Optimises Chip Production with Test Chip for Fault Localisation in Complex Semiconductor Processes - Joint Development with the Regensburg University of Applied Sciences
The development, production and also the practical deployment of the test chip were performed at Infineons site in Regensburg. The test chip is based on an innovative circuit concept developed by the Regensburg University of Applied Sciences. It has now been possible to demonstrate the full functionality. The test chip will initially be used in Infineons Regensburg-based wafer production facility and subsequently also at other production sites. Basically speaking, the new chip consists of a smart and universal addressing circuit, plus an array of test structures. The chip is based on a 0.35-µm CMOS process and is produced on 8-inch wafers. With its memory-like structure, the chip itself incorporates in excess of 1.2 million transistor functions on an area measuring only six square millimetres.
Infineon and the Regensburg University of Applied Sciences have been working together for a number of years now. The focus of this cooperation is the industry-oriented processing of a wide range of projects in correspondingly structured study groups, said Dr. Rainer Holmer, Head of Product and Process Technology for CMOS, BICMOS and RF Technologies at the Infineon sites in Regensburg, Villach and Munich. The development of this test chip under the direction of Professor Dieter Kohlert of the Regensburg University of Applied Sciences once again highlights just how successful the cooperation is between industrial enterprises, research and teaching.
How the test chip works
The newly devised test chip is to be used to test vias, i.e. the conductive connections between two metallized layers. Since the typical failure probability in an advanced CMOS process is only around 10 to 20 ppb (parts per billion) for the vias tested here, a sufficient quantity of test data is required in order to perform a statistical evaluation. For this purpose, the test chip features an array with 512 x 512 vias (262 144), along with the associated selection transistors for the addressing function. On just one wafer, 60 imaging blocks with 42 test chips each have been mapped, which equates to 2,500 test chips/wafer and as such around 640 million vias. Each via can be addressed individually, whilst its electrical resistance and the voltage drop at the via can be measured precisely.
The functionality of the test chip has been proven by using a tester to measure deliberately prepared via defects. Thanks to the addressing function, it was possible to locate the faults precisely on the chip. As such, the via/array test chip constitutes a highly sensitive test instrument for testing production processes within the via sector. Even the slightest of process changes affect the electrical response behaviour of the vias and can be registered by performing a simple measurement with the tester. The test chip concept is being further developed in cooperation with the Regensburg University of Applied Sciences so as to allow other process steps in the chip production sequence to be examined in a bid to ensure circuit reliability and enhanced productivity.
Infineon Technologies AG, Munich, Germany, offers semiconductor and system solutions for the automotive and industrial sectors, for applications in the wired communications markets, secure mobile solutions as well as memory products. With a global presence, Infineon operates in the US from San Jose, CA, in the Asia-Pacific region from Singapore and in Japan from Tokyo. In the fiscal year 2002 (ending September), the company achieved sales of Euro 5.21 billion with about 30,400 employees worldwide. Infineon is listed on the DAX index of the Frankfurt Stock Exchange and on the New York Stock Exchange (ticker symbol: IFX). Further information is available at www.infineon.com.