Infineon Technical Presentations at ISSCC 2003: Papers Highlight Cutting Edge Research in Biochips, Flexible Circuits, High-Speed Communications Chip Design and Memory Technology
Munich, Germany and San Francisco February 5, 2003 This edition of the Infineon Technologies (FSE/NYSE: IFX) News Alert service provides a synopsis of presentations by company researchers at the International Solid-State Circuits Conference (ISSCC 2003), a global forum for presentations of advances in solid-state circuits and Systems-on-a-Chip. ISSCC will take place on February 9-13, 2003 at the San Francisco Marriott Hotel.
Infineon Technologies researchers are well represented at this years conference, presenting seven separate papers across a wide range of topics. These include advances in new applications for CMOS chip technology, including bio-sensor array chips, flexible organic circuits, and smart textiles. The company is also presenting new developments in high-speed communications chips, and the results of two joint research projects in memory chip design. The titles, and short summaries, of each paper are listed here:
This paper from Infineons Corporate Research Center describes a Bio-Sensor Array Chip, which allows living cells to communicate with CMOS circuits. The chip provides 16,384 capacitive sensors in a 128 x 128 array on an area of 1 mm x 1 mm. A specifically adapted surface and chip design allows recording of extra-cellular signals from neural tissue, with sensitivity to electrical signals on the order of 100 microvolt (µV) 5 milliVolt (mV) (peak-to-peak). First biological lab measurements have been performed by Infineon's project partner, the Max-Planck-Institute for Biochemistry in Martinsried, Germany, using cells from a snail brain. The data reveal successful operation of the chip and demonstrate that Infineon's neurochip is capable of providing exciting new insights in the field of neurosciences. This technical breakthrough represents a scientific pathway to fast and statistically significant cell-based pharma screening.
Infineon researchers have developed a broad portfolio of processes that can be combined in a variety of ways and can be used to manufacture high-quality organic transistors and circuits using conventional chip making techniques, including deposition processes and photo-lithographic as well as printing patterning techniques. These processes work on flexible organic (and thus low-cost) polymer materials and even on ultra-low cost paper substrates. The paper presentation at ISSCC describes the development of circuit models and circuit design for the special requirements of polymer electronics. The developed model is accurate but very flexible, allowing rapid circuit and technology co-optimization for product design. An extrapolation assuming some reasonable future technology achievements shows the potential of the technology to reach circuit speeds of up to 150kHz.
A major step forward in integration of electronics into clothing will be described by Infineon researchers. They will present the seamless integration of electronics into clothing, based on packaging technology that allows the clothes to be washed or dry-cleaned without removal of the electronics. A demonstration system an MP3 player integrated into a jacket will be shown to illustrate the potential of this breakthrough technology. In addition Infineon will present a silicon-based micromechanical thermoelectric power generator that can harvest electrical energy from temperature differences.
The packaging technology for integration of electronics into textiles will open the way towards exploitation of a completely new field of electronics application. Logistics, consumer and medical application are prime areas addressed in the ongoing product development.
Recent advances in device scaling and doping profile optimization make it possible to implement SiGe (Silicon Germanium) bipolar transistors with impressive performance, such as cut-off frequencies in the range of 200 GHz and gate delays below 5 ps. This makes them an attractive choice for applications at 40 Gb/s and above. The presentation will focus on design aspects of high-speed SiGe circuits and discuss trade-offs between operating speed and power consumption. Circuit topologies and layout aspects of basic building blocks, such as logic gates, flip-flops, and multiplexers, are explored. Based on these circuit blocks, a fully integrated pseudo-random bit sequence generator is realized, which combines high functionality at high data rates with low power consumption.
A growing problem in design of high performance systems is that processor speeds are often bottlenecked by the limited ability to communicate off-chip to components such as memory, graphics displays, and disks. To maintain the historical trend of increasing processor computation-speed, off chip communication circuits (I/O) must also speedup. Infineon will present results of development of multiplexer/ demultiplexer circuts achieving data rates of 40Gb/s on a single wire. This new level in chip-to-chip communications for CMOS-base circuits demonstrates that the speeds wont be strangled by off-chip I/O, at least for the next few years.
This paper describes key circuit features of a FeRAM (Ferro-electric Random Access Memory) chip architecture. It allows for high memory density on small chip area with ultra low stand-by power dissipation. The FeRAM memory architecture combines the virtually infinite read/write endurance of DRAMs with the non-volatility of Flash memories resulting in an ideal and universal memory technology to support advanced mobile applications. The presented 32M Chain FeRAM is a joint development of Toshiba Corp., Japan, and Infineon Technologies.
The steadily increasing capacity of memory chips with large bit-line capacitances makes it difficult to maintain high access speed, particularly for SRAM (Static Random Access Memory). Current sense amplifiers are inherently faster than conventional voltage sensing because they avoid a large voltage swing across the capacitive bitlines. This paper is the first time presentation of a fully differential current sense amplifier that operates at supply voltages down to 0.7V. An efficient power-down capability together with fast and robust pre-charge eliminates the main obstacles for practical use of current sense amplifiers. An implementation on a 1.5V 4kx32-bit dual-port SRAM macro in 130nm CMOS has a measured access time of 1.7ns. This work is based on cooperation with the Institute for Technical Electronics of the Technical University Munich.
Infineon Technologies researchers are well represented at this years conference, presenting seven separate papers across a wide range of topics. These include advances in new applications for CMOS chip technology, including bio-sensor array chips, flexible organic circuits, and smart textiles. The company is also presenting new developments in high-speed communications chips, and the results of two joint research projects in memory chip design. The titles, and short summaries, of each paper are listed here:
New CMOS Chip Applications
- Paper 12.6 A 128 x 128 CMOS Bio-Sensor Array for Extracellular Recording of Neural Activity: February 11
This paper from Infineons Corporate Research Center describes a Bio-Sensor Array Chip, which allows living cells to communicate with CMOS circuits. The chip provides 16,384 capacitive sensors in a 128 x 128 array on an area of 1 mm x 1 mm. A specifically adapted surface and chip design allows recording of extra-cellular signals from neural tissue, with sensitivity to electrical signals on the order of 100 microvolt (µV) 5 milliVolt (mV) (peak-to-peak). First biological lab measurements have been performed by Infineon's project partner, the Max-Planck-Institute for Biochemistry in Martinsried, Germany, using cells from a snail brain. The data reveal successful operation of the chip and demonstrate that Infineon's neurochip is capable of providing exciting new insights in the field of neurosciences. This technical breakthrough represents a scientific pathway to fast and statistically significant cell-based pharma screening.
- Paper 21.6 - Evaluation of the Performance Potential of Organic TFT Circuits: Feb. 12
Infineon researchers have developed a broad portfolio of processes that can be combined in a variety of ways and can be used to manufacture high-quality organic transistors and circuits using conventional chip making techniques, including deposition processes and photo-lithographic as well as printing patterning techniques. These processes work on flexible organic (and thus low-cost) polymer materials and even on ultra-low cost paper substrates. The paper presentation at ISSCC describes the development of circuit models and circuit design for the special requirements of polymer electronics. The developed model is accurate but very flexible, allowing rapid circuit and technology co-optimization for product design. An extrapolation assuming some reasonable future technology achievements shows the potential of the technology to reach circuit speeds of up to 150kHz.
- Paper 22.1 Enabling Technologies for Disappearing Electronics in Smart Textiles: Feb. 12
A major step forward in integration of electronics into clothing will be described by Infineon researchers. They will present the seamless integration of electronics into clothing, based on packaging technology that allows the clothes to be washed or dry-cleaned without removal of the electronics. A demonstration system an MP3 player integrated into a jacket will be shown to illustrate the potential of this breakthrough technology. In addition Infineon will present a silicon-based micromechanical thermoelectric power generator that can harvest electrical energy from temperature differences.
The packaging technology for integration of electronics into textiles will open the way towards exploitation of a completely new field of electronics application. Logistics, consumer and medical application are prime areas addressed in the ongoing product development.
High-Speed Communications
- SE2 Design of SiGe Bipolar Circuits for 40+Gb/s Applications: Feb. 9
Recent advances in device scaling and doping profile optimization make it possible to implement SiGe (Silicon Germanium) bipolar transistors with impressive performance, such as cut-off frequencies in the range of 200 GHz and gate delays below 5 ps. This makes them an attractive choice for applications at 40 Gb/s and above. The presentation will focus on design aspects of high-speed SiGe circuits and discuss trade-offs between operating speed and power consumption. Circuit topologies and layout aspects of basic building blocks, such as logic gates, flip-flops, and multiplexers, are explored. Based on these circuit blocks, a fully integrated pseudo-random bit sequence generator is realized, which combines high functionality at high data rates with low power consumption.
- Paper 19.6 40 Gb/sec 2:1 Multiplexer and 1:2 Demultiplexer in 120nm CMOS: Feb. 12
A growing problem in design of high performance systems is that processor speeds are often bottlenecked by the limited ability to communicate off-chip to components such as memory, graphics displays, and disks. To maintain the historical trend of increasing processor computation-speed, off chip communication circuits (I/O) must also speedup. Infineon will present results of development of multiplexer/ demultiplexer circuts achieving data rates of 40Gb/s on a single wire. This new level in chip-to-chip communications for CMOS-base circuits demonstrates that the speeds wont be strangled by off-chip I/O, at least for the next few years.
Memory Chip Design
- Paper 16.3 A 32Mb Chain FeRAM with Segment / Stitch Array Architecture: Feb. 11
This paper describes key circuit features of a FeRAM (Ferro-electric Random Access Memory) chip architecture. It allows for high memory density on small chip area with ultra low stand-by power dissipation. The FeRAM memory architecture combines the virtually infinite read/write endurance of DRAMs with the non-volatility of Flash memories resulting in an ideal and universal memory technology to support advanced mobile applications. The presented 32M Chain FeRAM is a joint development of Toshiba Corp., Japan, and Infineon Technologies.
- Paper 26.3 A 1.5V, 1.7ns 4kx32 SRAM with a Fully-Differential Auto-Power-Down Current Sense Amplifier: Feb. 12
The steadily increasing capacity of memory chips with large bit-line capacitances makes it difficult to maintain high access speed, particularly for SRAM (Static Random Access Memory). Current sense amplifiers are inherently faster than conventional voltage sensing because they avoid a large voltage swing across the capacitive bitlines. This paper is the first time presentation of a fully differential current sense amplifier that operates at supply voltages down to 0.7V. An efficient power-down capability together with fast and robust pre-charge eliminates the main obstacles for practical use of current sense amplifiers. An implementation on a 1.5V 4kx32-bit dual-port SRAM macro in 130nm CMOS has a measured access time of 1.7ns. This work is based on cooperation with the Institute for Technical Electronics of the Technical University Munich.
About Infineon
Infineon Technologies AG, Munich, Germany, offers semiconductor and system solutions for the automotive and industrial sectors, for applications in the wired communications markets, secure mobile solutions as well as memory products. With a global presence, Infineon operates in the US from San Jose, CA, in the Asia-Pacific region from Singapore and in Japan from Tokyo. In fiscal year 2002 (ending September), the company achieved sales of Euro 5.21 billion with about 30,400 employees worldwide. Infineon is listed on the DAX index of the Frankfurt Stock Exchange and on the New York Stock Exchange (ticker symbol: IFX). Further information is available at www.infineon.com.
Information Number
INFCPR200302.040e