Optimizing PCB layout for GaN transistors

The fast switching speed of GaN transistors brings various advantages ranging from higher efficiency to power density but can make PCB layout more challenging.

For years, the standard solution has been to slow down the switching speed of power devices, coming at the cost of increased power consumption and reduced efficiency. Obviously, this solution is no longer ideal.

The Top 10 recommendations for PCB layout optimization at a glance

  1. Consider where current will flow during switching transistors
  2. Layout inductance may be critical in some parts of the circuit, but unimportant in others
  3. Minimize layout inductance by taking advantage of PCB layer pairs with thin dielectric
  4. Avoid deviations from the “over/under same path” that will result in lateral loops
  5. Package inductance ins not necessarily a fixed value for any SMT package
  6. Use top-side cooled SMT packages to optimize both electrical and thermal paths independently
  7. Use a plate for the return-path of gate-drive circuits
  8. Prevent capacitive currents
  9. Keep ground reference circuits away from high-side gate-drive circuit
  10. Keep the switch-node compact