Munich, December 04, 2006 – Multi-gate field-effect transistor technology appears to be an answer to many challenges down the road toward ever-smaller integrated circuits that retain high functionality while consuming considerably less energy than the planar single-gate technologies available today. In a demonstration of this new technology, researchers at Infineon have tested the world’s first complex circuit fabricated using a new 65nm multi-gate transistor architecture. With an approximately 30-percent smaller footprint compared to current single-gate technology with the same functions and performance, the new transistors had quiescent current that measured a factor of 10 less. According to the researchers' calculations, this will increase the energy efficiency and battery life of portable devices up to two times compared to the 65nm technology going into production today. For future technology nodes (32nm and beyond), this factor will increase significantly.
"With the world's first integrated circuit in 65nm multi-gate technology, we have proven that progress can be made in the semiconductor industry not only by simply continuing to scale down," said Prof. Dr. Hermann Eul, member of the Infineon Management Board and head of the Communication Solutions business group. "Today we are challenged to use the processes and materials available to us in a more innovative way to advance our technology as cost-efficiently as possible. Our researchers' results have been impressive indeed. And beyond that, based on the results so far, we expect that multi-gate technology could offer an excellent opportunity to continue CMOS device scaling into 32nm and below."
The 65nm circuitry tested by the Infineon researchers contains more than 3,000 active transistors fabricated in three-dimensional multi-gate technology. Results confirm that multi-gate is just as powerful as today's mature technologies, but consumes as little as half as much energy for the same functionality, an advantage that is certain to become increasingly important in enabling future technology generations.
Up to now, the semiconductor industry has accommodated customer demand for greater performance by regularly continuing to miniaturize transistors up to the limits of what is technologically feasible. This is the only way it has been possible to produce cell phones with integrated cameras, and super-flat MP3 players with huge storage capacities. However, the smaller the size of the integrated circuits, the larger the undesirable quiescent current, also known as leakage current, which leads to unnecessary energy consumption. Even when there is no activity present and the transistor is nominally "off," electrons still leak through the depletion potential barrier, which is only a few nanometers thick and only controlled from the surface by the single gate of the conventional planar transistor.
To be able to reliably switch individual transistors on and off and keep energy consumption to an absolute minimum despite continuing miniaturization, researchers at Infineon chose to innovate in a completely new direction: they changed the standard planar transistor architecture, which has been flat (two-dimensional) for the past 50 years, to form a three-dimensional structure. The third dimension is the key to success: the gate electrode of the transistor now encloses the depletion potential barrier on several sides (multi-gates), thus offering 3 times the contact surface to ensure that the transistor can be really switched off.
Conventional manufacturing processes and currently available materials can be used to build circuits in multi-gate technology on either bulk-silicon or silicon-on-insulator substrates, making their production independent of cost-intensive material innovations. Using the third dimension also opens up another remarkable advantage: with the same number of transistors on a chip, the amount of silicon actively used per transistor can be decreased, which saves material and cost.
Infineon will continue to explore the new manufacturing process, which could be ready for use as a basic technology in mass production in five to six years, partially in connection with its participation in the core partner program at IMEC (Interuniversity Micro Electronics Center, Leuven, Belgium), the European Research Center.