Munich, November 6, 2006 – Infineon has become the first semiconductor manufacturer in the world to introduce a method that can avoid one of the most common causes of defects in the production of highly integrated semiconductor circuits: the electrical failure of VIA contacts. "VIA" stands for "vertical interconnect" and refers to the contact between two metal layers in integrated circuits. Infineon developed the new method in collaboration with the Regensburg University of Applied Sciences (FH Regensburg) as part of its Automotive Excellence™ program, launched some three years ago to meet the automotive industry’s exacting quality requirements.
"Optimal security can only be ensured by delivering the highest product quality," notes Elfriede Geyer, Vice President Quality Management at the Automotive, Industrial & Multimarket Business Group of Infineon. "Our Automotive Excellence program aims to deliver zero-defect products and is the most comprehensive quality management program in the industry. What sets Infineon’s initiative apart from conventional quality management programs is its holistic approach, which includes elements such as production in company-owned facilities that have been specifically optimized for product quality. The core of our Automotive Excellence program is: No rework!“
Today's integrated circuits contain millions of transistors that are interconnected by several layers of metal wiring. The components known as “VIAs” connect the metal conductors between the layers. They are extraordinarily small: A VIA, manufactured in 0.13µm-Technologie, has a diameter of just 200 nanometers, which makes it about 300 times thinner than a human hair. A modern microcontroller of around half a square centimeter in size contains well in excess of ten million VIAs. There is no possibility to optically or electronically control or measure the quality of a VIA during the manufacturing process. Electrical failure of a single VIA can, in the most extreme case, impair the functionality of the entire microcontroller, causing suboptimal performance, even in applications that are critical to safety.
The VIA array test chip is typical of the holistic methodology employed by Infineon in the Automotive Excellence program. Infineon is the first semiconductor manufacturer in the world to develop a method that can reliably identify potential VIA failures with high probability. The findings clearly locate the corresponding sources of defects in the production chain and eliminate or circumvent them from the outset. The VIA test chip allows Infineon to reduce its VIA defects by a factor of around 10.
The test chip maps an arrangement of more than half a million VIA cells, with each cell containing both the VIA to be evaluated and the associated control electronics. The electrical resistance and voltage drop are measured and then used as parameters to establish whether a VIA is defective, and, if so, where the source of the defect lies.
Infineon is currently using the VIA test chip primarily for components being manufactured in 0.5µm and 130-nanometer technology, e.g. the AUDO NG microcontroller, which uses 130-nanometer embedded flash technology. Infineon is confident that the VIA test chip will also be suitable for future technologies such as 90- and 65‑nanometers. "The VIA test chip is a unique method for determining VIA reliability," Geyer resumes. "It lets us measure the reliability of VIAs by screening their quality on a permanent basis and by selectively analyzing conspicuous VIAs. That allows us to avoid defects right from the start. Infineon technologies perfected by VIA test chip monitoring will stand out from competing products thanks to their significantly higher quality, manifest in significantly lower dpm (defects per million).”
Besides making automotive applications even safer, the new VIA test method will also yield economic benefits for Infineon. For one, the company expects to drive down costs as fewer failure returns will occur. In addition, an optimal balance between chip/wafer surface and quality requirements can only be achieved if the anticipated failure rates per chip are known.