Infineon Presents Innovative Design and Circuit Concepts for Next Generations of Multimedia Communication Systems

Munich, February 9, 2006 – Infineon Technologies (FSE/NYSE: IFX), a leading supplier of advanced communication ICs and solutions, presented at the ISSCC 2006 (IEEE International Solid-State Circuits Conference) in San Francisco (February 4 - 8, 2006) several technical papers, in the context of 13 papers overall, describing important milestones on chip design for next generations of multimedia communication solutions. The introduced innovative advancements in circuit concepts will enable mobile broadband communication according to the requirements of future communication technologies.

Infineon underlined its leading technology position in communication ICs by presenting high-integrated wireless products as the world-wide first true quad-band single-chip GSM/GPRS radio and the industries first WiMedia/MBOA compliant UWB transceiver, both developed in standard CMOS technology. Furthermore Infineon described a high-performance 90nm GSM/EDGE baseband processor with special multimedia functions as a cost-effective low-power solution for feature phones. 

“The Communication Solutions Business Group of Infineon defines the future of communications by developing and manufacturing leading edge semiconductors and solutions for smooth transmission of telephony, high-speed data and television programs over all kind of network infrastructures to a broad variety of end users’ equipment”, stated Prof. Dr. Hermann Eul, member of the company’s management board and head of Infineon`s Communication Solutions Business Group. “With the presented papers Infineon shows again that it is well prepared to provide sophisticated silicon solutions for future generations of converging communications products, driven by performance, enhanced mobility, low power and reduced costs.”

Summary information on Infineon’s participation at ISSCC related to communications applications is given below by highlighting on advances in chip design for wireless communications technologies:

A fully integrated SoC for GSM/GPRS in 130nm CMOS

The first true single-chip radio for quad-band GSM/GPRS in standard 130nm CMOS technology integrates RF, analog/mixed signal functions, DSP (digital signal processor), application processor, RAM/ROM and audio. One of the greatest challenges to integrate digital logic and RF functionality in one single chip is crosstalk. The paper showed how crosstalk from digital to RF blocks was minimized to allow the single-chip implementation fulfilling the specifications for all bands and channels. The presented chip is the core device of a GSM mobile phone. Together with a power amplifier, power management IC, some switches and filters it makes up a complete quad-band GSM/GPRS handset.

A 90nm CMOS Low-Power GSM/EDGE Multimedia-enhanced Baseband Processor with 380MHz ARM9 Core and Mixed-Signal Extensions

The presented baseband IC integrates a high-performance 380MHz ARM926 processor core together with a TEAKlite DSP. Combined with special multimedia extensions like a 16bit HiFi audio front-end and analog/mixed-signal functions the chip represents a cost-effective solution for feature phones. Up to 40 percent reduced power consumption will enable significantly longer battery run times.

A WiMedia/MBOA-compliant CMOS RF Transceiver for UWB

UWB (Ultra-Wideband), a short-range radio technology for so-called personal area networks (WPAN), complements longer range radio technologies such as Wi-Fi or WiMAX and cellular wide area communications. It is used to relay data from a host device to other devices in the immediate neighborhood (up to 10 meters). The 130nm CMOS RF transceiver presented by Infineon is the first device that fulfills the WiMedia/MBOA (Multi-Band OFDM Alliance) requirements for UWB data communication in the 3-5GHz band. It shows significant improvements on transmission power (15dB) and noise figures (3.6 to 4.1dB) compared to previous CMOS and BiCMOS SiGe implementations.

In two papers Infineon described general developments in semiconductor design for key components for next generation communication systems:

A 10bit 10GHz digital controlled LC oscillator (DCO) in 65nm CMOS

DCOs are key components for the implementation of fully integrated digital PLLs (Phase Lock Loops) in RF transceivers e.g. for cellular phones. The chip presented by Infineon at ISSCC 2006 is the first DCO running at frequencies above 10GHz. Using new architectural and layout concepts the 65nm CMOS device achieves low power and high tuning performance. The DCO consumes only 3.0mA from a 1.1V supply.

A 14bit 100MS/s digitally self-calibrated Pipelined ADC in 130nm CMOS

Highly-integrated communication systems require high-speed, high-resolution Analog-to-Digital converters with low power consumption. In conventional pipelined ADCs the front-end S/H (sample/hold) and the first multiplying DAC consume the most power. The new ADC design presented by Infineon eliminates the need for a dedicated front-end S/H stage by using an innovative charge compensation scheme and therefore saves power. A new digital calibration architecture enables the usage of simple low-gain opamps even for high resolution. The proposed architecture operates from a 1.5V supply voltage and prepares the way to further reduced process geometries with even smaller supply voltages.