Infineon Technical Presentations at VLSI Symposium 2003: Papers Highlight Cutting Edge Development in MRAM and FeRAM Technologies and High-k Dielectrics for Next Chip Generations
At this years VLSI Technologies and Circuit conference five papers will be presented that highlights results obtained in the development of advanced semiconductor technologies: New results on the successful development of two nonvolatile memory technologies, Magnetoresistive RAM and Ferroelectric RAM, will be discussed in 3 papers. Two additional papers explain recent results on the integration of alternative high-k dielectrics in new process technologies.
The titles, and short summaries, of each paper are listed here:
Paper 13-1 - Bitline/Plateline Reference-Level-Precharge Scheme for High-Density ChainFeRAM
This paper describes key circuit features for further optimization of the Chain FeRAM (Ferro-electric Random Access Memory) chip architecture. This architecture allows for high memory density on small chip area with ultra low stand-by power dissipation. The novel circuit features, which significantly increase the signal margin and product yield, as well as the product reliability include a three-level plate line drive scheme for reduction of the gate oxide stress and a capacitive balancing scheme for increased signal margin, are presented. The FeRAM circuit schemes are implemented on a 32Mb Chain FeRAM product chip, which is a joint development of Toshiba Corp., Japan, and Infineon Technologies.
Paper 2-4 A 0.18 µm Logic-based MRAM Technology for High Performance Nonvolatile Memory Application
This paper discusses the fabrication of a 128Kb MRAM (Magnetoresistive Random Access Memory) using the worlds smallest MRAM cell size with only 1.4 square micron. The nonvolatile memory chip was fabricated on a standard 0.18 micron logic based process with three copper metallization layers and a 1T1MTJ (1 Transistor, 1 Magnetic-Tunnel-Junction) architecture. Repeated write cycles of the test array shows excellent endurance with no degradation through 630 million write cycles.
Paper 16-4 - A High-Speed 128Kbit MRAM Core for Future Universal Memory Applications
The paper describes a symmetrical high-speed sensing architecture using complementary reference cells and configurable load devices. Extrapolations of measurements from the 128Kbit MRAM test chip described in the above abstract and circuit assessments predict a 5ns random array read access time and random write operations with less than 5ns write pulse width. These results highlight the high performance capabilities of the 1T1MTJ architecture of the MRAM technology.
Paper 12A-1 Direct Measurement of the Inversion Charge in MOSFETs; Application to Mobility Extraction in Alternative Gate Dielectrics
Infineon, IBM, IMEC, KU Leuven, International Sematech, Institut für Halbleitertechnik TU-Darmstadt
Scaled MOSFETs using alternative gate dielectrics show strongly reduced carrier mobility. Conventional measuring techniques to determine the carrier mobility and the possible causes for the reductions are not reliable for FETs (Field Effect Transistors) with alternative gate dielectrics, because of strong charge trapping during the measurements.
This paper introduces Inversion Charge Pumping (ICP) as a new alternative method to measure the true inversion charge in n-channel FETs. The method was used to extract the mobility in FETs with conventional and SiO 2/HfO 2 dual layer gate dielectrics. It was demonstrated that charge trapping and net-fixed charge in n-channel MOSFETs are not the primary cause for the strong mobility degradation. This new measurement method with the related results on carrier mobility and charge trapping is a mayor step in the integration of new alternative dielectric materials in future CMOS chip technologies.
Paper 12A-3 Dynamics of Threshold Voltage Instability in Stacked High-k Dielectrics: Role of the Interfacial Oxide
Infineon, IBM, IMEC, International Sematech, KU Leuven
To fulfil high performance requirements as the feature size of future chip generations shrinks, a lot of effort is concentrated on research and development of high isolation (high-k) alternative dielectrics to replace conventional silicon oxide. It has been shown that observed threshold voltage instability in SiO 2/HfO 2 dual layer gate stacks can be explained by charging and discharging of pre-existing defects in the gate stack.
This paper demonstrates that the threshold voltage instability of the HfO 2 (Hafnium oxide) gate dielectrics is controlled by the dynamics of the electron trapping and detrapping in the HfO 2 bulk defects. Therefore the measured magnitude of the instability depends critically on the gate leakage, the electric field, the lattice temperature and the timing of the used measurement procedure. It is also shown that the interfacial oxide thickness influences the mechanism of charging and discharging of the HfO 2 defects. When the thickness is reduced, trap filling by electron tunnelling appears to contribute to the instability effects. So the bulk trapping properties of the HfO 2 layers have to be controlled - otherwise the threshold voltage instability threatens the high-k dielectric integration in future CMOS processes.
Infineon Technologies AG, Munich, Germany, offers semiconductor and system solutions for the automotive and industrial sectors, for applications in the wired communications markets, secure mobile solutions as well as memory products. With a global presence, Infineon operates in the US from San Jose, CA, in the Asia-Pacific region from Singapore and in Japan from Tokyo. In fiscal year 2002 (ending September), the company achieved sales of Euro 5.21 billion with about 30,400 employees worldwide. Infineon is listed on the DAX index of the Frankfurt Stock Exchange and on the New York Stock Exchange (ticker symbol: IFX). Further information is available at http://www.infineon.com