Infineon Technical Presentations at ESSCIRC 2003: Presented Papers Show New Circuit Developments for High Performance Communications Applications
At this years ESSCIRC conference six papers and one poster have been presented by Infineon that highlight results obtained in the development of advanced semiconductor technologies. The titles and short summaries of each paper are listed here:
A Fully Integrated 5.3GHz, 2.4V, 0.3W SiGe Bipolar Power Amplifier with 50 Ohms Output
This paper presents a radio frequency power amplifier for 4.8 - 5.7GHz realized in an advanced 0.35µm SiGe-bipolar technology. The balanced 2-stage push-pull power amplifier uses two on-chip transformers as input-balun and for interstage matching. Further three coils are integrated for the LC-output balun and the rf-choke. Thus the power amplifier does not need any external components. At supply voltages of 1.0V,1.5V, and 2.4V, output powers of 17.7dBm, 21.6dBm, and 25dBm are achieved at 5.3GHz. The respective power added efficiency is 15.6%, 22.4% and 24%. The small-signal gain is 26dB.
A 50GHz Direct Injection Locked Oscillator Topology as Low Power Frequency Divider in 0.13µm CMOS
An injection locked oscillator topology was presented in this paper, based on MOS-switches directly coupled to the LC-tank of well-known LC-oscillators. The direct injection locking scheme features a very low input capacitance and high frequency capability. The functionality of the direct locking is verified through two test circuits in 0.13µm standard CMOS. With a power consumption of only 3mW, one oscillator divides 50GHz by two with a locking range of 80MHz. Also at a power consumption of 3mW, the second oscillator with a lower Q tank divides 42GHz by two with a locking range of 1.5GHz.
A Quad-Band Low Power Single Chip Direct Conversion CMOS Transceiver with Sigma-Delta-Modulation Loop for GSM
This paper describes a fully integrated quad-band GSM transceiver with a new sigma-delta modulator architecture designed in a standard 0.13µm CMOS technology. The GSM specifications are fulfilled with a phase error below 1.6° over all bands. The fully integrated VCO operates at 4GHz with a frequency range that can be programmed by 10bit. The output power of the transmitter is 8dBm and no TX SAW filter is needed due to the low phase noise. The receiver has a constant gain of 57dB and fits to a baseband processor with a 14-bit ADC. The noise figure of the chip housed in a 48-pin VQFN package in all bands is typically below 3dB. The power consumption is only 210mW in transit mode and 250mW for the receiver.
Comparision of Distance Mismatch and Pair Matching of CMOS Devices
Distance mismatch and pair matching are compared for resistors and transistors of a 0,13µm CMOS technology. The device mismatch depending on the spatial distance between the devices is described using a statistical gradient parameter. This gradient parameter has to be taken into account for mixed signal circuit performance if short channel transistors or small width resistors are used. The gradient parameter is an increasing function of the critical device geometry parameter like the channel length. This paper gives a quantitative comparison of distance mismatch and pair mismatch. The results are basic inputs for circuit simulators and serve as guide lines for circuit design.
A 15MHz Bandwith Sigma-Delta ADC with 11 Bits of Resolution in 0.13µm CMOS
A wide bandwidth continuous time Sigma-Delta ADC implemented in a 0.13µm CMOS technology was presented. Active blocks are composed of regular threshold voltage devices only. The circuit is targeted for wide-bandwidth applications such as video or wireless base-stations. The 4th-order architecture uses an OpAmp-RC based loop filter and a 4bit internal quantizer. Operated at 300MHz clock frequency, the converter achieves a dynamic range of 11 bits, bandwidth is 15MHz. At 1.5V supply voltage the power dissipation is 70mW.
A 20Gb/s 82mW One-Stage 4:1 Multiplexer in 0.13µm CMOS
In this paper a completely integrated 4:1 multiplexer for high speed operation and low power consumption in 0.13µm CMOS was presented. The circuit uses a new architecture where four data streams are multiplexed in one stage. Pulses with 25% duty cycle select inputs to appear at the MUX-output. The lower number of gates enables low power design. Relaxed timing conditions are additional benefits of the one-stage MUX topology. The MUX works from DC up to 20Gb/s and consumes only 82mW.
A 10-Bit, 3mW Continuous-Time Sigma-Delta ADC for UMTS in a 0.13µm CMOS Process
In this presentation a 10bit-resolution continuous-time multibit Sigma-Delta ADC for UMTS was described. A power-efficient implementation of a 3rd-order multi-bit modulator is presented: By using a feedforward architecture and quantizer dynamic element matching the dissipated power can be reduced. Clocked at 104MHz, the 0.13µm CMOS Sigma-Delta ADC achieves 60dB peak SNR at 2MHz signal bandwidth, consuming only 3mW at 1.2V supply voltage.
Infineon Technologies AG, Munich, Germany, offers semiconductor and system solutions for the automotive and industrial sectors, for applications in the wired communications markets, secure mobile solutions as well as memory products. With a global presence, Infineon operates in the US from San Jose, CA, in the Asia-Pacific region from Singapore and in Japan from Tokyo. In fiscal year 2002 (ending September), the company achieved sales of Euro 5.21 billion with about 30,400 employees worldwide. Infineon is listed on the DAX index of the Frankfurt Stock Exchange and on the New York Stock Exchange (ticker symbol: IFX). Further information is available at http://www.infineon.com.