Infineon Technologies Announces 0.18 micron Embedded DRAM Process Technology for Customized System-on-Chip
Munich/Germany May 22, 2000 Infineon Technologies AG (FSE/NYSE: IFX), a global leader in CMOS application specific standard products (ASSPs), today announced its C10DE 0.18 micron drawn gate length embedded DRAM process technology for customized System-on-Chip solutions. The new C10DE platform process technology supports the integration of logic and analog functions together with embedded DRAM (eDRAM) on one chip without compromising logic and analog speed, density or functionality.
The C10DE state-of-the-art process technology is the next step in Infineons strategy to offer system level integration (SLI) ASICs for networking and telecom systems (switches, routers and base stations), digital consumer products (3G mobile phones and PDAs), and computer peripherals (DVD drives and printers) among others.
Our new C10DE embedded DRAM technology enables our customers to design true system level integration solutions with the advantages of reduced form factor, power consumption, system cost, and improved performance, stated Dietmar Baier, Director of ASIC Marketing at Infineon Technologies. Additionally, our C10DE eDRAM macros are fully integrated into our semi-custom ASIC design flow, making it very easy for the experienced ASIC designer to use them.
Because C10 is a platform process technology, the logic portion of C10DE is identical to Infineons C10N 0.18 micron gate length CMOS logic process technology with up to 6 layers of copper interconnect. All of Infineons C10N Intellectual Property (IP), including microcontroller cores such as the 16-bit C166S, the 32-bit TriCore Unified Processor and Carmel DSP cores, application specific IP cores like E1/T1, HDLC, ISDN and xDSL, analog functions such as PLLs, ADCs and DACs, as well as third party IP like ARM7 and ARM9 processor cores may also be integrated in the C10DE process technology. Trench capacitor embedded DRAM macros are designed for easy integration into a SLI ASIC design flow. A full set of library views and models, along with simple, straightforward memory interfaces and built-in self test (BIST) structures enable designers to decrease design time as well as production and development costs.
C10DE offers the flexibility to configure the on-chip embedded DRAM modules in one Mbit increments. This fine granularity and scalability allows system designers to define application-optimized solutions addressing the specific area, power consumption and cost targets of their system application.
Data Input/Output (I/O) width of 256 bits and maximum access frequency of up to 150 MHz supports transfer rates up to 5 Gigabytes/second per embedded DRAM macro. This enables the design of high performance system architectures required for applications ranging from datacom routers and switches to computer peripherals. Discrete DRAMs typically do not allow the same performance in terms of speed and bandwidth that embedded DRAMs can support.
The C10DE is available in sample quantities and production volume is planned for early Q4 2000. SXMaker ASIC design toolkits for C10DE are currently available.
Further information regarding Infineon ASIC technology is available at www.infineon.com/asic
The C10DE state-of-the-art process technology is the next step in Infineons strategy to offer system level integration (SLI) ASICs for networking and telecom systems (switches, routers and base stations), digital consumer products (3G mobile phones and PDAs), and computer peripherals (DVD drives and printers) among others.
Our new C10DE embedded DRAM technology enables our customers to design true system level integration solutions with the advantages of reduced form factor, power consumption, system cost, and improved performance, stated Dietmar Baier, Director of ASIC Marketing at Infineon Technologies. Additionally, our C10DE eDRAM macros are fully integrated into our semi-custom ASIC design flow, making it very easy for the experienced ASIC designer to use them.
Because C10 is a platform process technology, the logic portion of C10DE is identical to Infineons C10N 0.18 micron gate length CMOS logic process technology with up to 6 layers of copper interconnect. All of Infineons C10N Intellectual Property (IP), including microcontroller cores such as the 16-bit C166S, the 32-bit TriCore Unified Processor and Carmel DSP cores, application specific IP cores like E1/T1, HDLC, ISDN and xDSL, analog functions such as PLLs, ADCs and DACs, as well as third party IP like ARM7 and ARM9 processor cores may also be integrated in the C10DE process technology. Trench capacitor embedded DRAM macros are designed for easy integration into a SLI ASIC design flow. A full set of library views and models, along with simple, straightforward memory interfaces and built-in self test (BIST) structures enable designers to decrease design time as well as production and development costs.
C10DE offers the flexibility to configure the on-chip embedded DRAM modules in one Mbit increments. This fine granularity and scalability allows system designers to define application-optimized solutions addressing the specific area, power consumption and cost targets of their system application.
Data Input/Output (I/O) width of 256 bits and maximum access frequency of up to 150 MHz supports transfer rates up to 5 Gigabytes/second per embedded DRAM macro. This enables the design of high performance system architectures required for applications ranging from datacom routers and switches to computer peripherals. Discrete DRAMs typically do not allow the same performance in terms of speed and bandwidth that embedded DRAMs can support.
The C10DE is available in sample quantities and production volume is planned for early Q4 2000. SXMaker ASIC design toolkits for C10DE are currently available.
Further information regarding Infineon ASIC technology is available at www.infineon.com/asic
About Infineon
Infineon Technologies AG, Munich, Germany, offers semiconductor solutions for applications in the wireless and wired communications markets, for the automotive and industrial sectors, for security systems and chip cards as well as memory products. With a global presence, Infineon operates in the US from San Jose, CA, and in the Asia-Pacific region from Singapore. In the fiscal year 1999 (ending September), the company achieved sales of Euro 4.24 billion (US $ 4.51 billion) with about 26,000 employees worldwide. The company is listed on the main market segment (Amtlicher Handel) of the Frankfurt Stock Exchange and at the New York Stock Exchange. Further information is available at www.infineon.com
Infineon, the stylized Infineon Technologies design are trademarks of Infineon Technologies AG. All other trademarks are the property of their respective owners.
Any statements in this document that are not historical facts are forward-looking statements that involve risks and uncertainties; actual results may differ from the forward-looking statements. Infineon Technologies undertakes no obligation to publicly release the results of any revisions to these forward-looking statements that may be made to reflect events or circumstances after the date hereof or to reflect the occurrence of unanticipated events.
Information Number
INFCP200005.062e