EZ-PD™ PAG1P Primary Side Controller
Secondary-side controlled primary start-up controller
EZ-PD™ PAG1P is a primary start-up controller designed to work with EZ-PD™ PAG1S in a secondary side-controlled flyback converter. EZ-PD™ PAG1P provides the HV start-up function, PET receiver, low-side NFET gate driver, high-side logical level driver, and fault protection (line UVP/OVP, OCP, secondary VBUS startup OVP). It supports both X-cap discharge mode and non-X-cap discharge mode.
- Integrated high-voltage start-up
- Integrated low-side gate driver
- Line UVP and OVP
- Support primary OCP
- Startup secondary VBUS OVP
- Support non/X-cap discharge
- Programmable soft-start
- Integrated PET receiver
Once the line voltage is within normal operating range, the gate driver starts switching. An internal high-voltage JEFT takes current from the HV pin to charge up the VCC capacitor during the start-up phase. An auxiliary winding from the flyback transformer will be used to supply EZ-PD™ PAG1P after the start-up phase and no current will be sourced from the HV pin after the start-up phase. The soft-start feature allows EZ-PD™ PAG1P to gradually increase the output voltage of the flyback converter until the secondary side takes control of the regulation. Soft-start is used during initial start-up sequence and fault condition. The duration of the soft-start is controlled by an external capacitor connected to the SS pin and the frequency of the soft-start is determined by an external resistor connected to the RT pin. An internal current source of 5 µA charges the external capacitor and the maximum amplitude for the soft-start ramp is 3.75 V. 3.75 V dictates the maximum duty cycle. Under soft-start, the maximum ON time of the primary FET is limited to 19 µs, which is equivalent to 70% duty cycle at 30 kHz. When the secondary side takes control, the maximum ON time is limited to 25 µs.
In EZ-PD™ PAG1P x-cap part, x-cap mode is detected when 3 V_VDD700UVRISE transitions occur within 64 ms. A flag is set indicating the part is operating in x-cap mode. When 3 V_VDD700UVRISE transitions are not detected within 64 ms after the flag is set, a line disconnect is detected and an internal discharge path is turned ON to discharge the x-capacitor. For the non x-cap discharge mode, the HV pin is connected to the DC rectified voltage. The pin powers EZ-PD™ PAG1P during startup. Additionally, it provides under-voltage and overvoltage protection via the HV pin. As long as the fault is present, protection is enabled.
During the start-up phase, if EZ-PD™ PAG1P sees appropriate input pulses at the PULSEIN pin, then it synchronizes the primary FET control to the secondary pulses. The PWM control signal from the secondary side is coupled to the primary side using a Pulse Edge Transformer (PET). The PET is an important component to ensure proper frequency response and should have just an adequate Q-factor to avoid excessive overshoot. The positive pulse from the PET is treated as primary FET turn-on signal and the negative pulse from the PET is treated as primary FET turn-off signal. The pulse amplitude shall not exceed V_PULSEINNEGAMP and V_PULSEINPOSAMP and the pulse width shall be within T_PULSEINPW range. The synchronization path between the secondary and primary through the PET is also used for communication of shutdown condition. Three consecutive negative pulses from the secondary side is treated as a shutdown signal. On receiving such three consecutive negative pulses, EZ-PD™ PAG1P will shutdown after 200 ms.
