Our overall goal is to combine the low R_DS(on) offered by silicon carbide MOSFETs with an gate drive mode in which the device operates in the safe oxide field-strength conditions. Consequently, it was decided to focus on trench-based devices moving away from a planar surface with high-defect density towards more favorable surface orientations. The latter enabling a low channel resistance at low oxide fields. These boundary conditions are the baseline for transferring quality assurance methodologies established in the silicon power semiconductor world in order to guarantee FIT rates expected in industrial and even automotive applications.

Infineon is the world’s first commercial Silicon Carbide (SiC) device supplier. Long market presence and experience enable Infineon to deliver highly reliable, industry-leading SiC performance. The differences in material properties between Silicon Carbide and Silicon limit the fabrication of practical Silicon unipolar diodes (Schottky diodes) to a range up to      100 V–150 V, with relatively high on-state resistance and leakage current. In SiC material Schottky diodes can reach a much higher breakdown voltage. The Infineon portfolio of Silicon Carbide (SiC) products covers 600 V and 650 V to 1200 V Schottky diodes.

In case of SiC to reduce FIT rates (quantifying hard fails) - two influencing factors must be considered:

• Cosmic ray effects (same as for Si devices)
• Gate oxide reliability (due to the oxide field stress)

Cosmic ray stability is usually achieved by optimizing the electric field distribution in the drift zone. However, to bring oxide FIT rates down, effective screening of electrically active defects is required. Principally, Si and SiC MOSFETs have pretty much the same intrinsic oxide lifetime as long as the devices do not contain defect-related impurities, i.e. extrinsic defects. SiC MOSFETs exhibit a much higher extrinsic defect density in the gate oxide, in contrast to Si MOSFETs. Devices with extrinsic defects break down earlier in comparison to defect-free devices. The challenge to guarantee sufficient reliability of the gate oxide of SiC MOSFETs is to reduce the number of devices being affected by extrinsics by means of electrical screening. Each device is subjected to a gate stress pattern - destroying those with critical extrinsics. As a consequence, the enabler for an efficient gate oxide screening is a nominal oxide thickness that is much higher than is typically needed to fulfill the intrinsic lifetime targets, what leads to a trade-off between gate-oxide-FIT-rate and device performance.