High speed, High performance Synchronous SRAMs
Sync SRAMs is a type of volatile random-access memory (RAM) that uses flip-flop based latching circuitry to store each bit. The data bits are retained in memory as long as power is supplied. Unlike Async SRAM, Sync SRAMs has a clocked interface for control, address and data. Infineon provides the Industry’s broadest portfolio of Synchronous SRAMs from 2M to 144M.
Infineon’s Sync SRAMs are RoHS compliant, QML certified for Defense products and available in industry standard TSOP, BGA, SOP packages.
Density:2M,4M, 9M, 18M, 36M, 72M, 144M
Interface: Parallel (x8, x16, x32, x72)
- Highest RTR - Industry leading Random Transaction Rate of 2132 MT/s
- High reliability - On-Chip ECC to provide lowest Soft error rate <0.1FIT/Mbit
Infineon offers a comprehensive portfolio of Sync SRAMs including Standard Sync SRAM, NoBL™ SRAM, DDR/QDR SRAM.
- Standard Sync SRAMs: These were created especially for cache applications. They incorporate an internal 2-bit burst counter that supports a cache line size of four and are available in densities ranging from 2 Mbit to 72 Mbit.
- No Bus Latency (NoBL™) Sync SRAMs: Commonly known as Zero bus Turn-around (ZBT) SRAMs, they require no idle cycles when the bus is turned around, that is, when it transitions from Read to Write, or Write to Read. Two versions of NoBL SRAM exist: Flow-through and Pipelined. NoBL Flow-through SRAMs always have a one clock cycle delay from address to data in the system. Pipelined NoBL SRAM requires an additional pipelined register in the device output. These are available in densities ranging from 2 Mbit to 144 Mbit.
- DDR-II/II+/II+ Xtreme Sync SRAMs: DDR stands for Dual Data Rate. DDR-II SRAMs have common Read and Write ports. These are similar to the legacy Synchronous Burst SRAM products but with double data rate I/Os. They are suitable for read intensive functions such as packet look up and packet classification in networking/ communication applications.
- QDR-II/II+/II+ Xtreme Sync SRAMs: QDR stands for Quad Data Rate. QDR-II SRAMs were developed to address network applications that require the low latency and full cycle utilization of NoBL SRAMs but also require a significantly higher operating frequency. QDR-II SRAMs have separate Read and Write buses. QDR SRAM memories are available in densities ranging from 18 Mbit to 144 Mbit
- QDR-IV Sync SRAMs: The QDR-IV SRAMs are high-performance memory devices optimized to maximize the number of random transactions per second by the use of two independent bidirectional data ports. QDR SRAMs are used in networking applications where reads and writes are balanced such as packet buffer, statistics counters, flow state, and scheduling. They are available in 72 Mbit and 144 Mbit densities with the Random Transaction Rate (RTR) required for 100-400 Gigabit line cards in switches and routers
Random Transaction Rate (RTR) is the number of fully random read or write transactions a memory can perform every second. It is measured in MT/s, or mega transactions per second. RTR is a critical metric in high-performance computing, general-purpose servers, and image-processing applications., where memory access is unpredictable.
The QDR consortium defined QDR™ (Quadruple Data Rate) SRAM products are geared primarily to the networking and communication market. QDR SRAMs allows access to any two memory locations on every clock cycle, and performance never depends on which memory location was accessed in the previous clock cycle. Hence, with QDR SRAM, RTR is guaranteed.
QDR-IV SRAMs are capable of operating in burst-of-two or banked burst-of-two modes, which deliver the fastest clock speeds and highest RTR of all QDR SRAMs and also higher than competing RLDRAMs and DDR3 DRAMs.
Infineon's QDR-IV SRAM provides RTR up to 2132 MT/s.