Infineon's Asynchronous SRAMs offer High speed, Low power with on-chip ECC to suit a variety of applications
Async SRAM is a type of Volatile random-access memory (RAM) that uses flip-flop based latching circuitry to store each bit. The data bits are retained in memory as long as power is supplied. Infineon provides the Industry’s broadest portfolio of Asynchronous SRAMs from 256K to 64M. Async SRAMs are used in Networking, Defence and Industrial applications due to its High reliability and Long Term Support offered. MoBL Asynchronous SRAMs are also ideal for battery powered and battery-backed solutions (BBSRAM) across a range of application segments that require data backup on power loss.
Infineon’s Async SRAMs are RoHS compliant, QML certified for Defence products and available in industry standard TSOP. BGA, SOP packages.
Density: 256K,512K,1M,2M,4M,8M,16M,32M, 64M
Interface: I2C | SPI | QSPI | Parallel (x8, x16, x32)
- Fast access - Fastest access time as low as 10ns
- Low Power - Powersnooze™ option for energy efficient operation
- High reliability - On-Chip ECC to provide lowest Soft error rate <0.1FIT/Mbit.
- Long term support for SRAM parts
Our Async FAST SRAMs are industry’s fastest parallel Async SRAM solutions with fastest access time of 10ns. These are available in densities ranging from 64Kbit – 32Mbit supports wide voltage range from 1.8V to 5V. These are used in applications such as networking applications such as switches and routers.
Our Async Micropower (MoBL®) SRAMs are most energy efficient Async SRAM solutions with Powersnooze™ mode. These are available in densities ranging from 256Kbit – 64Mbit supports wide voltage range from 1.8V to 5V. These are used in battery powered and battery-backed solutions.
Infineon’s Asynchronous SRAM memories combine the access time of Fast Asynchronous SRAM with a unique ultra-low-power sleep mode into one chip through the Powersnooze™ feature. This feature lets SRAMs to operate at fast speeds of 10ns (100 MHz), while consuming < 2 µA / Mbit (typ.) of sleep current. By invoking this “deep sleep” feature, SRAM’s quickly transition from a high-speed active state to a power saving sleep state. This ensures that the full power of your MCU to be harnessed, since the SRAM is no longer the limitation to achieving your peak performance. Read this Application Note to learn more about the Powersnooze™ feature.
Systems running mission-critical applications need memories with zero system errors. Higher energy extra-terrestrial radiations such as Alpha particles, thermal neutrons, Cosmic rays can flip multiple adjacent bits, leading to multi-bit errors.
Our Asynchronous SRAMs use (38,32) hamming code ECC for single-bit error detection and correction and performs all ECC related functions in line, without user intervention. SRAMs with ECC are form-fit-function compatible with older generation Asynchronous SRAMs. This allows you to improve system reliability without investing in PCB re-design.
A Multibit upset is a type of radiation-induced upset identified when two or more flipped bits are physically adjacent or have a separation of, at most, one non-failing bit. Bit-interleave distance separates two consecutive bits mapped to the same word register. In a bit-interleaved memory, a single-bit error correction algorithm can be used to detect and correct all errors. Together, these features provide significant improvement in Soft Error Rate (SER) performance, resulting in industry’s most reliable SRAMs with <0.1 FIT/Mbit.
Battery Backed SRAM's (BBSRAM's), also called NVRAM's are used in applications that require any kind of data backup in the event of a power failure. In these cases, we can use a conventional SRAM memory along with a back-up battery and control circuitry to create a fast, non-volatile memory. Infineon also offers FRAM and nvSRAM non-volatile memories for applications requiring higher endurance and longer retention.
Read this Application Note to understand the design considerations that need to be considered for using Async SRAM in battery backed applications.