Work to be performed

eRamp will combine research, development and innovation on enhanced, next generation methodologies for design, reliability and productivity to leverage smart power pilot lines.

In order to strengthen the competitiveness of the European semiconductor industries, it is of substantial importance to shorten learning cycles for implementing new technologies and products into production. This issue will be addressed through manifold innovations:

• Work on improved metrology for fast identification of device critical parameters; methods to extract independent, uniform distributions out of device characterization data for e.g. Monte Carlo simulations

• Work on enhanced methodologies for fast and efficient learning related to device physical constraints and yields

• Work on new methods to transfer variability and reliability information over different levels of abstraction

• Work on new methods for reliability predictions based on small quantity manufacturing volumes

• Work on faster simulations to handle complex circuits and large number of influencing parameters as well as methods to handle non-uniform distributions

• Work on new production tools and technologies to enable the realization of next generation MtM semiconductors

 

• Research on enhanced, next generation yield and reliability learning to leverage smart power pilot lines and 3D systems integration

• Enhance the core competencies of European companies in the MtM semiconductor development as well as the ability for production at competitive cost in Europe, thus also supporting the EU KET initiative by pilot line

• Set up collaborative value chain(s) in MtM semiconductor system and device design

• Development of manufacturing chains which provide the take up of KETs such as nanotechnology for the realization of novel 3D-integrated devices

• Leverage rapid time to market by enhanced methodologies in fast yield and reliability learnings

• Use user-centered design/development (UCD) approaches defining the demonstrators according to application needs providing optimized methods and knowledge centered innovation

• High speed simulation environment for comprehensive large circuit simulation with focus on Monte Carlo methodology

• Combine semiconductor MtM technology with innovative assembly and packaging for optimum chip/package integration of power semiconductors that does not use any wire bonding or flip chip bonding

• Set-up of an assembly and packaging pilot line for integration of power semiconductors chips with lowest parasitic and best heat dissipation. Lowest parasitic lead to best energy efficiency