F4-17MR12W1M1HP_B76 CoolSiC™ MOSFET fourpack module 1200 V

Overview

EasyPACK™ 1B CoolSiC™ MOSFET fourpack module 1200 V, 17 mΩ G1 with NTC, pre-applied thermal interface material (TIM) and PressFIT contact technology.

Summary of Features

  • Best-in-class packages with 12 mm height
  • Leading edge WBG material
  • Very low module stray inductance
  • Enhanced CoolSiC™ MOSFET Gen 1
  • Enlarged gate drive voltage window
  • Gate-source voltages of +23 V and -10 V
  • Tvjop under overload condition up to 175°C
  • PressFIT pins
  • Integrated NTC temperature sensor
  • Thermal Interface Material (TIM)

Benefits

  • Outstanding module efficiency
  • System cost advantages
  • System efficiency improvement
  • Reduced cooling requirements
  • Enabling higher frequency
  • Increase of power density
Diagrams
Videos

Customers of power electronics require ever more modern, easy connection technologies, which also provide a higher reliability to meet the trends to higher temperatures and new applications.

Training

Introduction to SiC reliability

This training covers the properties of Silicon Carbide which change the way how an inverter is designed compared to Si-chips. With that in mind, we explain SiC specific degradation mechanisms and how to ensure that SiC devices survive in the application, considering these special failure modes, by applying the reliability tests Infineon developed. These are internally mandatory for SiC device qualifications to ensure better quality, safety, and reliable device performance for years.

With the growing market of electrical vehicles, the industry has put forward more requirements for the performance of charging piles.

This e-learning will show you that the emergence of CoolSiC™ MOSFETs has improved the charging pile industry to make the EV charger smaller, faster and with higher efficiency.

With this training you will learn how to calculate a reference gate resistance value for your Silicon Carbide MOSFET, how to identify suitable gate driving ICs based on peak current and power dissipation requirements and to fine-tune the gate resistance value in laboratory environment based on worst case conditions.

Support