C166®S V1 Architecture & Core

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C166®S V1 Architecture & Core

The C166®S V1 is an enhanced member of the Infineon family of full featured 16-bit single-chip microcontrollers. It combines high CPU performance with high peripheral functionality. Several key features contribute to the high performance of the C166®S V1 (the indicated timings refer to a CPU clock of 100 MHz):

High Performance 16-Bit CPU With Four-Stage Pipeline

  • 20 ns minimum instruction cycle time, with most instructions executed in 1 cycle

  • 100 ns multiplication (16-bit *16-bit), 200 ns division (32-bit/16-bit)

  • Multiple high bandwidth internal data buses

  • Register based design with multiple variable register banks

  • Single cycle context switching support

  • 16 MBytes linear address space for code and data (von Neumann architecture)

  • System stack cache support with automatic stack overflow/underflow detection

Control Oriented Instruction Set With High Efficiency

  • Bit, byte, and word data types

  • Flexible and efficient addressing modes for high code density

  • Enhanced boolean bit manipulation with direct addressability of 6 Kbits for peripheral control and user defined flags

  • Hardware traps to identify exception conditions during runtime

  • HLL support for semaphore operations and efficient data

  • access

External Bus Interface

  • Multiplexed or demultiplexed bus configurations

  • Segmentation capability and chip select signal generation

  • 8-bit or 16-bit data bus

  • Bus cycle characteristics selectable for five programmable address areas

16-Priority-Level Interrupt System

  • Up to 112 interrupt nodes with separate interrupt vectors

  • 16 priority levels and 4(8) group levels

Up to 16-Channel Peripheral Event Controller (PEC)

  • Interrupt driven single cycle data transfer

  • Transfer count option (std. CPU interrupt after programmable number of PEC transfers)

  • Long Transfer Counter

  • Channel Linking

  • Eliminates overhead of saving and restoring system state for interrupt requests

C166®S V1 Architecture & Core

Application Notes

Title Size Date Version
544 KB 02 Jan 2012

User Manual

Title Size Date Version
3.2 MB 22 Jul 2015 01_06
1.6 MB 03 Jan 2012 02_00

C166®S V1 Architecture & Core

C166®S V1 Architecture & Core

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