Synchronous SRAM

• Highest RTR - Industry leading Random Transaction Rate of 2132 MT/s
• High reliability - On-Chip ECC to provide lowest Soft error rate <0.1FIT/Mbit

Infineon offers a comprehensive portfolio of Sync SRAMs including Standard Sync SRAM, NoBL™ SRAM, DDR/QDR SRAM.

• Standard Sync SRAMs: These were created especially for cache applications. They incorporate an internal 2-bit burst counter that supports a cache line size of four and are available in densities ranging from 2 Mbit to 72 Mbit.
• No Bus Latency (NoBL™) Sync SRAMs: Commonly known as Zero bus Turn-around (ZBT) SRAMs, they require no idle cycles when the bus is turned around, that is, when it transitions from Read to Write, or Write to Read. Two versions of NoBL SRAM exist: Flow-through and Pipelined. NoBL Flow-through SRAMs always have a one clock cycle delay from address to data in the system. Pipelined NoBL SRAM requires an additional pipelined register in the device output. These are available in densities ranging from 2 Mbit to 144 Mbit.
• DDR-II/II+/II+ Xtreme Sync SRAMs: DDR stands for Dual Data Rate. DDR-II SRAMs have common Read and Write ports. These are similar to the legacy Synchronous Burst SRAM products but with double data rate I/Os. They are suitable for read intensive functions such as packet look up and packet classification in networking/ communication applications.
• QDR-II/II+/II+ Xtreme Sync SRAMs: QDR stands for Quad Data Rate. QDR-II SRAMs were developed to address network applications that require the low latency and full cycle utilization of NoBL SRAMs but also require a significantly higher operating frequency. QDR-II SRAMs have separate Read and Write buses. QDR SRAM memories are available in densities ranging from 18 Mbit to 144 Mbit
• QDR-IV Sync SRAMs: The QDR-IV SRAMs are high-performance memory devices optimized to maximize the number of random transactions per second by the use of two independent bidirectional data ports. QDR SRAMs are used in networking applications where reads and writes are balanced such as packet buffer, statistics counters, flow state, and scheduling. They are available in 72 Mbit and 144 Mbit densities with the Random Transaction Rate (RTR) required for 100-400 Gigabit line cards in switches and routers

Random Transaction Rate (RTR) is the number of fully random read or write transactions a memory can perform every second. It is measured in MT/s, or mega transactions per second. RTR is a critical metric in high-performance computing, general-purpose servers, and image-processing applications., where memory access is unpredictable.
The QDR consortium defined QDR™ (Quadruple Data Rate) SRAM products are geared primarily to the networking and communication market. QDR SRAMs allows access to any two memory locations on every clock cycle, and performance never depends on which memory location was accessed in the previous clock cycle. Hence, with QDR SRAM, RTR is guaranteed.

QDR-IV SRAMs are capable of operating in burst-of-two or banked burst-of-two modes, which deliver the fastest clock speeds and highest RTR of all QDR SRAMs and also higher than competing RLDRAMs and DDR3 DRAMs.
Infineon's QDR-IV SRAM provides RTR up to 2132 MT/s.

Infineon works with chipset partners to qualify Infineon memories with partner SoCs. Chipset partners get early access to Infineon products and dedicated support to qualify our memories on their boards. These efforts result in pairing charts that map our Infineon memory products with chipset partner product portfolios. The table below contains links to the pairing charts. Select a memory from these pairing charts to shorten your design cycle.

Chipset pairing charts:

• Map Infineon memory products with our chipset partner portfolios
• Indicate for each SoC, the supported memory interfaces
• Highlight both recommended memories and qualified memories
• Indicate (when applicable) which software version has been qualified

Infineon IC qualification with an SoC is performed by our SoC partner via a reference design, evaluation board, bring-up board, demonstration board, validation board, or turnkey reference design.

Guidelines for how to use chipset pairing charts: 

• Use them to select the best Infineon solution(s) for your chipset of choice
• Use them to fine-tune the selection of Infineon solutions (compliant memory interface, voltage, memory density, etc.)

Get in Touch

Do you have a question about pairing Infineon memory with a particular chipset, whether or not referenced on our site? Do you have a more generic question about Infineon memory support with a given chipset partner? Please Get in Touch with us!