SRAM (Static RAM)

With On-Chip Hardware ECC (Error Correction Code), Infineon’ SRAMs perform all ECC related functions in line, without intervention. Higher energy extra-terrestrial radiation can flip multiple adjacent bits, leading to multi-bit errors. The single-bit error detection and correction capability of ECC is supplemented by a bit-interleaving scheme to prevent the occurrence of multi-bit errors. Together, these features provide significant improvement in Soft Error Rate (SER) performance, resulting in industry leading FIT rates of less than 0.1 FIT/Mbit. Infineons Asynchronous SRAM memory products are classified into two families based on their access time:

• Low-power Asynchronous SRAMs: These are devices that typically operate in the 45-ns and slower speed range. These SRAMs are typically designed to consume very low power and are used in applications where power is a major concern. They are often used for temporary data storage and scratch pad applications. Infineon’ MoBL® Micropower Asynchronous SRAMs belong to this family.
• Fast Asynchronous SRAMs: These are devices that typically operate in the sub–25 ns region. They are often used in buffer and cache memory applications. Infineon offers Fast SRAMs with PowerSnooze™ to offer devices that combines the access time of Fast Asynchronous SRAM with a unique ultra-low-power sleep mode

Synchronous SRAM memory products are classified based on the data transfer rates:

• Single Data Rate SRAMs: These are synchronous SRAMs where one word of data is transferred between the SRAMs and the controller in a given clock cycle. These include Infineon’ Pipelined SRAMs, Flowthrough SRAMs, Burst SRAMs and Network SRAMs – NoBL™/ZBT™ SRAMs
• Double & Quad Data Rate SRAMs: These SRAMs can transfer multiple data words in a given cycle. These SRAMs are designed to be the SRAMs of choice for networking applications with high data rate requirements. QDR (Quad Data Rate™) and DDR (Double Data Rate) SRAMs belong to this family.

SRAM uses a flip-flop based latching circuitry to store each bit. Nearly all SRAMs either use a 4-Transistor or a 6-Transistor memory cell. These cell structures allow data to be stored for an indefinite amount of time in the device as long as it is powered. SRAMs come in two different flavors: Synchronous and Asynchronous. Synchronous SRAMs are devices that are synchronized with an external signal called a clock. The device will read and write information into the memory only on particular states of the clock. An asynchronous SRAM, on the other hand, does not depend on the state of a clock. It will begin to read or write information into the memory as soon as it receives the instruction to do so.

SRAMs don’t require period refresh like DRAMs, hence offer better performance. A DRAM cell is composed of an access transistor and a capacitor. Data is stored in the capacitor as electrical charge, but the electrical charge leaks over time. Therefore, DRAM must be refreshed periodically to preserve the stored data. The refresh negatively impacts DRAM performance and power dissipation. Due to this, SRAMs are also typically faster and have lower power consumption than DRAMs.

Infineon works with chipset partners to qualify Infineon memories with partner SoCs. Chipset partners get early access to Infineon products and dedicated support to qualify our memories on their boards. These efforts result in pairing charts that map our Infineon memory products with chipset partner product portfolios. The table below contains links to the pairing charts. Select a memory from these pairing charts to shorten your design cycle.

Chipset pairing charts:

• Map Infineon memory products with our chipset partner portfolios
• Indicate for each SoC, the supported memory interfaces
• Highlight both recommended memories and qualified memories
• Indicate (when applicable) which software version has been qualified

Infineon IC qualification with an SoC is performed by our SoC partner via a reference design, evaluation board, bring-up board, demonstration board, validation board, or turnkey reference design.

Guidelines for how to use chipset pairing charts: 

• Use them to select the best Infineon solution(s) for your chipset of choice
• Use them to fine-tune the selection of Infineon solutions (compliant memory interface, voltage, memory density, etc.)

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Do you have a question about pairing Infineon memory with a particular chipset, whether or not referenced on our site? Do you have a more generic question about Infineon memory support with a given chipset partner? Please Get in Touch with us!