Active and preferred
RoHS Compliant
Lead-free

S80KS2564GACHV040

Data Sheet
package
ea.
in stock

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

S80KS2564GACHV040
S80KS2564GACHV040
ea.
Data Sheet

Product details

  • Density
    256 MBit
  • Family
    KS-4
  • Interface Frequency (SDR/DDR) (MHz)
    - / 200
  • Interfaces
    HYPERBUS x16
  • Lead Ball Finish
    Sn/Ag/Cu, Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 105 °C
  • Operating Voltage range
    1.7 V to 2 V
  • Operating Voltage
    1.8 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    See roadmap
  • Qualification
    Industrial
  • Technology
    HYPERRAM
Recommended
OPN
S80KS2564GACHV040
Product Status active and preferred
Infineon Package
PG-BGA-49
Package Name FBGA-49 (002-32552)
Packing Size 260
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-BGA-49
Package Name FBGA-49 (002-32552)
Packing Size 260
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
S80KS2564GACHV040 is a 256 Mb HYPERRAM™ self-refresh DRAM (PSRAM) with a 1.8 V HYPERBUS™ extended-IO (x16) DDR interface. It supports up to 200 MHz clock, up to 800 MBps (6,400 Mbps) throughput, and 35 ns maximum access time. The device operates from 1.7 V to 2.0 V and –40°C to +105°C, and includes Hybrid Sleep, Deep Power Down, configurable bursts, and RWDS-based refresh latency indication.

Features

  • HYPERBUS extended-IO x16 bus
  • DDR transfers both clock edges
  • 200 MHz maximum clock rate
  • Up to 800 MBps data throughput
  • Maximum access time tACC 35 ns
  • Optional differential clock CK/CK#
  • RWDS strobe and write data mask
  • Configurable linear or wrapped burst
  • 1.7 V to 2.0 V VCC/VCCQ supply
  • Hybrid sleep retains memory data
  • Deep power down stops refresh
  • ESD: 2 kV HBM, 500 V CDM

Benefits

  • x16 DDR boosts bandwidth per pin
  • 800 MBps enables fast frame buffer
  • 35 ns tACC cuts read latency
  • Diff clock improves noise margin
  • RWDS eases timing and data mask
  • Burst modes optimize host traffic
  • 1.8 V supply fits modern MCUs
  • Hybrid sleep saves power, keeps data
  • DPD minimizes energy when unused
  • ESD ratings improve handling yield
  • Overshoot spec eases SI margins
  • Active clock stop reduces ICC level

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }