ASIC Design Flow is a highly automated approach applying state-of-the-art deep submicron design
methodologies such as early floor planning, links-to-layout, timing driven placement and routing.
The first time right claim is backed by design-for-test measures such as full scan design, ATPG
(Automatic Test Pattern Generation), BIST (Built-in Self Test), macro isolation with boundary scan,
IDDQ testing etc. Tight time-to-market cycles are met by using advanced verification methods such as
static timing analysis, formal verification and well defined sign-off procedures for all techologies.
For the various design steps we use industry leading, commercially available tools. Our emphasis
on standard interfaces and tools simplifies integration with the customer design flow tremendously.
We ensure continuous learning on design-flow and technology and implement regular updates
of our design system and libraries based on latest silicon results.