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Silicon-carbide MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) – we at Infineon offer them under the brand name CoolSiC™ – combine high performance with robustness and ease of use. They provide a high efficiency due to low switching losses and allow therefore a high power density. Nevertheless, designers need to understand the static and the dynamic performance of a device and the key parameters influencing them to achieve their design goals. In the paragraphs following, we will provide you with more insights into that.
Temperature influences the static performance in the first quadrant
The key parameter of the static output characteristic of a MOSFET is the total drain-source on-resistance RDS(on). We define its typical value for a CoolSiC™ MOSFET at room temperature and for a gate-source voltage (VGS) of 15 V and at the rated nominal DC current, as described on the left of figure 1. The threshold voltage VGS(th) follows the physics of the device and drops with temperature as shown in figure 1 on the right.
Figure 1: The output characteristics of an example 45 mΩ 1200 V CoolSiC™ MOSFET for room temperature and 175°C (left) and its dependence of Ron and VGS(th) on temperature (right)
The clearly positive temperature coefficient of the on-resistance visible on the right side of figure 1, which is an outcome of the low-channel defect density, makes the devices predestined for paralleling. This is another significant difference to DMOS (Double-Diffused Metal-Oxide-Semiconductor) components. These usually show a weaker dependence of the resistance on the temperature because of their high density of defects in the channel.
This DMOS “feature” sounds attractive at first glance. However, with progress towards lower on- resistances, the physically justified positive temperature dependence of the drift zone will increasingly dominate the total on-resistance. Thus, SiC MOSFETs will become more silicon-like. But we should note that even in a mature state the actual temperature coefficient of SiC MOSFETs would be lower than for silicon devices at the same blocking voltage. This is a result of their higher absolute doping densities. Furthermore, the temperature dependence of the on-resistance will be more pronounced for higher blocking voltages because of the increasing contribution of the drift zone to the total resistance. Figure 2 outlines the qualitative behavior.
Figure 2: The principal behavior of a MOSFETs on-resistance as a function of temperature and a comparison between silicon and SiC. The impact of the blocking voltage is shown as well.
Synchronous rectification improves the static performance in the third quadrant
In contrast to IGBTs (Insulated Gate Bipolar Transistors), a vertical MOSFET such as the CoolSiC™ device offers conduction in reverse mode via the body diode, which is practically a freewheeling diode. However, due to the band gap of SiC, the knee voltage of this diode is with around 3 Volts relatively high. This means that a continuous operation will result in high conduction losses. Consequently, it is mandatory for designers to use the well-known synchronous rectification concept. The diode is working just for a short dead time as a diode. After this period, the channel is turned on again by applying a positive VGS like in the first quadrant mode.
This operation scheme offers very low conduction losses in the third quadrant mode, since no knee voltage is in place, achieving the same resistance as in the first quadrant mode. In fact, the resistance is even slightly lower. This is because the impact of the JFET (Junction Field-Effect Transistor) is reduced due to a negative feed-forward impact of the now inverted current flow direction. Figure 3 illustrates the third quadrant operation as I-V characteristic for different gate voltages. Please note that due to the p-n diode structure a certain pulse current handling capability, which may be higher than in forward mode, can also be achieved.
Figure 3: The I-V behavior of the body diode for a 45 mΩ CoolSiC™ MOSFET
Capacitances determine the dynamic performance of SiC-MOSFETs
Being a unipolar device, the capacitances of a SiC MOSFET determine to a large extend its dynamic performance. The device was designed to have a small gate-drain reverse capacity Crss compared to the input capacity Ciss. This is beneficial for suppressing parasitic re-turn-on and can therefor prevent the use of sophisticated gate driver circuitry when operated in a half-bridge configuration. Many CoolSiC™ MOSFETs can be turned off safely even if 0 V is applied to the gate, since in addition to the favorable capacitance ratio the threshold voltage is sufficiently high. The left graph in figure 4 summarizes the component capacitances as a function of VDS.
The right side of figure 4 displays the typical switching losses of a half bridge with single devices mounted in a 4-pin TO-247 housing as a function of the drain current. The turn-off energy Eoff depends only slightly on the load current, since it is dominated by capacities. In contrast, the turn-on energy Eon increases linearly with current, and dominates the total losses Etot. Based on the status from mid-2019, we should emphasize that the CoolSiC™ MOSFET shows the lowest Eon among the commercially available 1200 V SiC MOSFETs. Eon and Eoff are nearly independent of temperature. Important to note is the fact that the actual housing design has a significant impact on switching losses, mainly on turn-on losses. Especially effective is the use of Kelvin contacts, which practically separate the load path from the control path in terms of current. Therefore, they help to prevent di/dt induced feedback loops to the gate signal which increase the dynamic losses.
Figure 4: The typical device capacitance vs. drain-source voltage for a 45 mΩ CoolSiC™ MOSFET (left) and the related switching energies (right) as a function of the drain current (for VGS = 15/-5 V, RG_ext = 4.5 Ω, VDS = 800 V, Tvj = 175°
In general, it is essential to implement fast-switching SiC transistors with low capacitances and gate charges only in certain packages. Major criteria include good thermal performance because of the high-loss power density (SiC of course reduces the absolute losses, but the remaining ones concentrate in tiny areas). Another criterion is a low stray inductance for managing high di/dt slopes without critical voltage peaks. Finally, especially for multi-chip packages with more die in parallel, a symmetric inner layout based on the strip line concept [1] is mandatory. Current module packages offering such features are our Easy platform for modules, or the TO-247 family, respectively TO263-7, for discrete housing.
The gate charge curve for CoolSiC™ MOSFETs is usually different from the typical shape of silicon power devices. In particular, there is no clear Miller plateau visible, as shown on the left side of figure 5. The total gate charge Qtot amounts to typically 75 nC for ID = 30 A, VDS = 800 V and RG_ext = 3.3 kΩ at VGS(off) = -5 V to VGS(on) = 15 V.
Often, there might be a need to adapt the switching speed (dv/dt) in order to deal with oscillations, etc. One benefit of MOSFETs is the simple way of adjusting the slopes via the gate resistor. Combined with the right driver circuit, it may even be different for turn-on and turn-off. Figure 5 on the right displays the corresponding behavior for our 45 mΩ 1200 V CoolSiC™ MOSFET.
Figure 5: A typical gate charge curve for a 45 mΩ 1200 V CoolSiC™ MOSFET (left) and the controllability of the switching speed via RG,ext (right)
Figure 6 depicts at the right the short-circuit waveforms for two 45 mΩ 1200 V CoolSiC™ MOSFETs: one in a 4-pin and the other one in a 3-pin TO-247 package. The figure shows both at a DC voltage of VDS = 800 V. The response of the devices differs significantly from the IGBT. Initially, the drain current increases rapidly and reaches a current peak. Because of the reduced feedback loop in the Kelvin-source design, the current of the MOSFET in the 4-pin TO-247 package rises faster. It also shows less self-heating at the beginning of the short-circuit event, with the high peak current exceeding 300 A. In contrast, the device in the 3-pin TO-247 package exhibits a smaller peak current. The major reason for this is a negative feedback which is induced by the di/dt against the applied VGS in the case of the 3-pin component. Since the Kelvin connection solution, which enables faster switching, eliminates this effect, the current can also rise to higher values for the 4-pin device before the saturation effect takes place.
After peak current, the drain current decreases down to about 150 A. This is because of the reduction in carrier mobility and a more pronounced JFET effect due to a temperature increase by self-heating. The test waveform shows a clean and robust behavior, which proves the typical 3 μs short-circuit capability for both packaged TO-247 CoolSiC™ MOSFETs. For power modules, the short-circuit capability is currently up to 2 μs according to the related target application requirements. Our CoolSiC™ MOSFETs are the first devices with a guaranteed short-circuit withstand time in the data sheets.
Figure 6: A typical short circuit as a function of duration time at 25°C (left) and the avalanche behavior of a 1200 V device, turn-off of an unclamped inductive load of 3.85 mH at 60 V (right)
An avalanche rating in the data sheet accompanies the new 650 V class devices to meet the demands of the target-application power supplies. In general, the CoolSiC™ MOSFET technology shows high ruggedness under avalanche. Figure 6 depicts on the right the typical behavior of a 1200 V component.
References
[1] P. Friedrichs, R. Bayerer SiC high power devices – challenges for assembly and thermal management, Materials Science Forum, Vols. 740–742, pp. 869–872, 2013