Hybrid switched-capacitor (HSC) – intermediate bus converter
Next generation two-stage resonant converter- hybrid switched-capacitor (HSC) converter topology
In resonant converters like the LLC, the switching frequency needs to be close to the LC resonance for soft switching. Moreover, the entire energy is transferred through the transformer, increasing the overall losses. A converter topology whose efficiency varies heavily with the component mismatch is not viable for mass production without extra compensation efforts. To overcome these issues a novel approach based on the HSC topology two-stage resonant converter is proposed by Infineon. As illustrated in the picture the HSC is formed by 6 MOSFETs divided into two legs, connected through two flying capacitors and a magnetic device called a multi-tapped autotransformer (MTA). The MTA is formed out of 4 windings connected in series sharing the same magnetic core. High-frequency operation is enabled by ZVS operation with the magnetizing inductance of the MTA.
The HSC provides an unregulated voltage rail which depends on the turn ratio between N1 and N2. The topology is driven by two symmetrical PWMs: H (i.e., Q1, Q3 and Q5 are ON with Q2, Q4 and Q6 OFF) and L (i.e., Q1, Q3 and Q5 are OFF with Q2, Q4 and Q6 ON). An introduced dead-time between the states enables load-independent ZVS operation. The HSC can run above- and below-resonant frequency without influencing the ZVS operation. Therefore, the overall system performance can be kept at a high level regardless of component tolerances. One of the key enablers for high efficiency and high power density of the HSC is the use of low-voltage rated MOSFETs with better figure of-merits (FOMs). For example, in an 8:1 configuration running from a 48 V rail, 25 V-rated MOSFETs for Q3 and Q6 can be used.
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One of the biggest bottlenecks in enabling AI and keeping up with the calculation and storage needs in the cloud is power management. More specifically, the power density of the power converters used to fuel the processors and ASICs in the system. The “Open Compute Project” (OCP) attempts to address these challenges by defining new standards in the power architecture, moving from the traditional 12 V intermediate bus voltage up to 48 V. This significantly reduces transmission losses and enables a more efficient way to transfer power to the payload (i.e., AI ASIC / GPU / CPU or SOC). The power levels of AI accelerator modules are already exceeding 750 W with currents as high as 1000 A (@ 0.75 V core voltage). When looking at as many as eight of those modules on one mainboard, the power ratings and thermal management efforts become mind-boggling.