Infineon Lays Foundation for New Industry Standard Package Technology

Nov 12, 2007 | Market News

Neubiberg, Germany, and Kaohsiung, Taiwan, November 12, 2007 – Infineon Technologies, a leading supplier of semiconductor and system solutions, and Advanced Semiconductor Engineering Inc. (ASE), the world’s largest semiconductor packaging and test company, today announced a partnership to introduce semiconductor packages with a higher integration level of package size with an almost infinite number of contact elements. This new package form achieves a 30-percent reduction of dimension compared to conventional (lead-frame laminate) packages.

Semiconductor pattern sizes are continuously shrinking to permit the implementation of more complex and efficient semiconductor solutions. Although the chip becomes smaller, the need for adequate connection space has imposed physical constraints on package shrinkage.

Infineon has now succeeded in extending the benefits of Wafer-Level Ball Grid Array (WLB) technology – namely, cost-optimized production and enhanced performance features – by a new technology, embedded WLB (eWLB). All operations are performed highly parallel at wafer level, as with WLBs, signifying concurrent processing of all the chips on the wafer in one step. To promote these advantages, Infineon and ASE have forged a partnership uniting the technology developed by Infineon with the packaging know-how of ASE in a license model.

"We are pleased Infineon has selected ASE as their IC packaging partner of choice in the introduction of this dynamic and leading-edge technology," stated Dr. Ho-Ming Tong, Chief R&D Officer, ASE Group. "Through this collaboration, we believe Infineon will significantly benefit from ASE’s packaging expertise and global market leadership, and we look forward to playing a part in their success."

“We will use our development to set the stage for future package generations and are responding to future market demands and keeping Moore’s Law in mind. As smaller pattern sizes and increasing performance require new, innovative approaches,“ said Prof. Dr. Hermann Eul, member of the Management Board of Infineon Technologies AG and head of the Communications Solutions Business Group. “Our trend-setting package technology sets the benchmark in integration level and efficiency. Together with ASE, we pave the way to providing the industry and end consumers with a new generation of energy-efficient, high-performing mobile devices.”

eWLB process

The eWLB technology is a forward-looking development of the WLB technology, upholding the known benefits such as small package dimensions, excellent electrical and thermal performance, and maximum connection density. However, this technology significantly increases the functionality and application spread. Due to eWLB, complex semiconductor chips such as modem and processor chips for applications in mobile communications require a high number of solder connections with standardized contact spacing to be produced with a minimal footprint. At the same time, the packages can be provided with as many solder contacts as needed. The possibility of additional wiring area around the chip proper means that the wafer-level packaging technology also lends itself to new, space-sensitive applications.

The new packages will be manufactured at the production sites of Infineon Technologies and at ASE under a license model. The first components are expected to be commercially available by the end of 2008.

About Infineon

Infineon Technologies AG, Neubiberg, Germany, offers semiconductor and system solutions addressing three central challenges to modern society: energy efficiency, communications and security. In fiscal year 2006 (ending September), the company achieved sales of Euro 7.9 billion (including Qimonda sales of Euro 3.8 billion) with approximately 42,000 employees worldwide (including approximately 12,000 Qimonda employees). Infineon is listed on the Frankfurt Stock Exchange and on the New York Stock Exchange (ticker symbol: IFX).

Information Number


Press Photos

  • Due to eWLB all operations are performed highly parallel at wafer level.
    Due to eWLB all operations are performed highly parallel at wafer level.

    JPG | 438 kb | 1535 x 1063 px