Infineon Presents Innovative Circuit Concepts for the Next Generation of High-Speed Communication Systems
Four-Channel Analog Front End for ADSL2+ Requires Only 75 mW per ChannelThe widespread ADSL (Asymmetric Digital Subscriber Line) standard for wireline communications was expanded a few months ago with the new ADSL2+ standard. Thanks to these changes, ADSL now uses a frequency range up to 2.2 MHz for the signal from the network to the terminal (downstream), with the option of an extended range that can exceed 4 MHz. This enables much higher data rates on short loops, which establishes the foundation for completely new applications. The Analog Front End (AFE) chip presented by Infineon in the ISSCC paper supports the new ADSL2+ standard, and all of the important parameters have been optimized. This circuit is a mixed-signal chip with very little power dissipation, and it is implemented in 0.13 µm CMOS technology. The AFE offers four channels and contains all the required functionalities: analog and digital codec blocks, filters, and a 14-bit A/D (analog-to-digital) and D/A (digital-to-analog) converter. A high level of integration, an extremely low level of power dissipation (just 75 mW per channel), a small silicon area and good manufacturability provide the basis for extremely efficient system solutions for all of the new ADSL standards. With regard to the accuracy of the A/D and the D/A converters, the linearity of the receive and transmit path, and the power consumption levels, the IC developed by Infineon offers twice the efficiency of ADSL analog chips introduced to date.
Power-Optimized, 14-Bit SC Delta-Sigma Modulator for ADSLInfineon is introducing an extremely high-performance A/D converter (ADC) featuring 130 nm CMOS technology. The ADC was developed for an ADSL line card solution for use in central offices (exchanges). These applications require high-resolution ADCs with large bandwidths, and they represent crucial functions within an ADSL chipset. On the other hand, power consumption is often the limiting factor in the design of highly integrated ADSL line cards. The chip surface area required for the new ADC (and thus also the cost) and the low level of power dissipation (8 mW with a 1.5 V supply and operation at 105 MHz) for the circuit developed by Infineon are significantly lower than that of the ADCs released so far for ADSL applications.
The ADC uses delta-sigma modulation. Besides a high level of oversampling, the existing noise power is also shaped spectrally in order to achieve a high resolution of 14 or 13 bits, with a corresponding signal bandwidth of 276 kHz or 1.5 MHz. The switched-capacitor design that is employed enables a robust implementation, since the relative accuracy of integrated capacitors can be produced with good consistency during manufacturing. Modern CMOS technologies work with reduced supply voltages; this lowers the achievable signal amplitude and represents a special challenge for the mixed-signal development of this type of ADC. Infineons solution is based on a reengineered topology that benefits the signal flow to an extent that is sufficient to compensate for the disadvantage of a reduced supply voltage.
Completely Integrated CMOS PLL Circuit with 13 GHz OutputIn this case, the circuit developed by Infineon is a special Phase Locked Loop (PLL) that was engineered in a cooperative project involving Infineons Villach Development Center in Austria and Corporate Research in Munich, Germany. This PLL has the highest output frequency (13 GHz) of all CMOS-based circuits reported to date. Until now, it was only possible to realize such high-frequency PLLs using bipolar technology. The fact that such a chip can now be built using CMOS technology makes it possible to integrate the transmitter, receiver and digital signal processing on a single chip for future high-frequency communication systems, thus creating the basis for inexpensive system solutions.
PLLs are used, for instance, in frequency synthesis, which converts a lower frequency to a higher frequency through multiplication by a factor of N. Here, Sigma-Delta Fractional-N technology also permits multiplication by a non-integer value N without having to accept any performance losses. In this way, the output frequency can be programmed in much smaller increments. The overall power consumption of the 13 GHz PLL is just 60 mW with a 1.5-V supply voltage. Such high frequencies are required for future wireline and wireless communication systems with high data rates. One example of an application is a research project for a wireless local area network (WLAN) chipset with wireless transmission in the 17 GHz frequency band. Here, the PLL delivers the basic clock pulse for both the transmitter and the receiver.
10-bit CMOS A/D Converter with 80 MHz and New Algorithms for Wireless LANBaseband processors for the new WLAN standards demand high-speed CMOS A/D converters. The employment of CMOS and reduced chip areas are indispensable especially for portable and cost-sensitive applications in order to meet the performance requirements while simultaneously ensuring low levels of power dissipation. Infineon presented a 10-bit pipeline ADC with 80 MHz that requires only 22 mA at 1.5 V. This made it possible to reduce the power consumption by approximately 50% compared to similar designs. Implemented in 130 nm CMOS technology, the complete circuit requires a chip area of only 0.3 mm 2, which leads to significant cost reductions. This performance increase was achieved on the basis of a conventional 1.5-bit pipeline architecture through the use of two new algorithms: Dynamic Range Doubling (DRD) and Dynamic Reference Selection (DRS).