Infineon at ESSDERC 2003 - Numerous Technical Presentations Demonstrate Infineons Strong Research and Development Activity
Lisbon, Portugal September 29, 2003 This year´s European solid state device research conference (ESSDERC) took place in Lisbon, Portugal from September 16 to 18. It is the annual meeting where micro and nano electronic devices are presented with a focus on novel and scaled CMOS devices, high-K, RF-CMOS, non-volatile memories, power devices and (bio-) sensors.
Infineon was actively present at ESSDERC with several technical presentations and an invited plenary talk on emerging non-volatile memory technology. In addition, the Best Paper Award of last years ESSDERC has been given to Infineon´s contribution Passive DNA Sensor with Gold Electrodes fabricated in a CMOS Backend Process.
In the following, the titles and brief summaries of some technical presentations are listed.
Infineon presented research results on the leakage mechanisms in fully depleted SOI (Silicon On Isolator) devices with undoped channels. Compared to conventional bulk transistors these devices exhibit larger on-currents; this, however, comes at the cost of being more sensitive to leakage effects. The results shows that within energy balance calculations the higher leakage currents can be attributed to band-to-band tunneling and impact ionization effects. Using adequate transistor design the leakage effects can be suppressed.
Scanning Spreading Resistance Microscopy (SSRM) is an AFM (Atomic Force Microscope) based carrier profiling technique. By measuring the spreading resistance, SSRM provides reliable information about the 2D doping profile and effective gate lengths of the devices. The presented SSRM measurements are in excellent agreement with TEM and electrical measurements. SSRM measurements resolve spatial resolution of < 3nm and can meet the ITRS requirements for the spatial resolution of 2D carrier profiling.
Test structures of novel nonvolatile memories based on charge trapping in atomic layer deposited aluminum oxide were presented and the main physical parameters validated by experiments. In contrast to the well-known Fowler-Nordheim programmable oxide-nitride-oxide memories, here, aluminium oxide acts as trapping dielectric or as a control gate dielectric. In this way, more then 20 percent smaller equivalent oxide thicknesses are achieved compared to todays charge trapping memories. Furthermore, key properties such as retention time and erase efficiency can be improved with appropriate design in comparison to state of the art oxide-nitride-oxide memories.
This paper described the technical aspects of Infineon´s Neuro-Chip. An high-k extended CMOS process was presented for recording of extracellular neural activity in a high-density sensor array. With the highly sensitive sensor array it is possible to measure the extremely low voltages (in the range of some 100 Microvolts) of nerve cells. A bio-compatible dielectric was used to couple nerve cell-induced biological signals to the CMOS circuitry below the sensor. The transducer consists of a multi-layer of TiO 2 and ZrO 2 and was fabricated in the backend of a 0.5 µm standard CMOS technology. Living cells were cultured within a specific package on top of the sensor chip.
A measurement technique has been presented to determine the self-heating of advanced bipolar heterojunction transistors. Contrary to most other methods it is especially well-suited for the investigation of many different transistors, making it useful for automated measurements during production. As another benefit, the emitter resistance is estimated as well. The technique has already been successfully used for both SiGe and GaAs HBTs.
Infineon was actively present at ESSDERC with several technical presentations and an invited plenary talk on emerging non-volatile memory technology. In addition, the Best Paper Award of last years ESSDERC has been given to Infineon´s contribution Passive DNA Sensor with Gold Electrodes fabricated in a CMOS Backend Process.
In the following, the titles and brief summaries of some technical presentations are listed.
Drain Leakage Mechanisms in Fully Depleted SOI Devices with Undoped Channel
Infineon presented research results on the leakage mechanisms in fully depleted SOI (Silicon On Isolator) devices with undoped channels. Compared to conventional bulk transistors these devices exhibit larger on-currents; this, however, comes at the cost of being more sensitive to leakage effects. The results shows that within energy balance calculations the higher leakage currents can be attributed to band-to-band tunneling and impact ionization effects. Using adequate transistor design the leakage effects can be suppressed.
Characterization of Ultra-thin SOI Transistors Down to the 20nm Gate Length Regime with Scanning Spreading Resistance Microscopy (SSRM)
Scanning Spreading Resistance Microscopy (SSRM) is an AFM (Atomic Force Microscope) based carrier profiling technique. By measuring the spreading resistance, SSRM provides reliable information about the 2D doping profile and effective gate lengths of the devices. The presented SSRM measurements are in excellent agreement with TEM and electrical measurements. SSRM measurements resolve spatial resolution of < 3nm and can meet the ITRS requirements for the spatial resolution of 2D carrier profiling.
Retention Time of Novel Charge Trapping Memories Using Al 2O 3 Dielectrics
Test structures of novel nonvolatile memories based on charge trapping in atomic layer deposited aluminum oxide were presented and the main physical parameters validated by experiments. In contrast to the well-known Fowler-Nordheim programmable oxide-nitride-oxide memories, here, aluminium oxide acts as trapping dielectric or as a control gate dielectric. In this way, more then 20 percent smaller equivalent oxide thicknesses are achieved compared to todays charge trapping memories. Furthermore, key properties such as retention time and erase efficiency can be improved with appropriate design in comparison to state of the art oxide-nitride-oxide memories.
Technology Aspects of a CMOS Neuro-Sensor: Backend Process and Packaging
This paper described the technical aspects of Infineon´s Neuro-Chip. An high-k extended CMOS process was presented for recording of extracellular neural activity in a high-density sensor array. With the highly sensitive sensor array it is possible to measure the extremely low voltages (in the range of some 100 Microvolts) of nerve cells. A bio-compatible dielectric was used to couple nerve cell-induced biological signals to the CMOS circuitry below the sensor. The transducer consists of a multi-layer of TiO 2 and ZrO 2 and was fabricated in the backend of a 0.5 µm standard CMOS technology. Living cells were cultured within a specific package on top of the sensor chip.
A Practical Method to Extract the Thermal Resistance for Heterojunction Bipolar Transistors
A measurement technique has been presented to determine the self-heating of advanced bipolar heterojunction transistors. Contrary to most other methods it is especially well-suited for the investigation of many different transistors, making it useful for automated measurements during production. As another benefit, the emitter resistance is estimated as well. The technique has already been successfully used for both SiGe and GaAs HBTs.
About Infineon
Infineon Technologies AG, Munich, Germany, offers semiconductor and system solutions for the automotive and industrial sectors, for applications in the wired communications markets, secure mobile solutions as well as memory products. With a global presence, Infineon operates in the US from San Jose, CA, in the Asia-Pacific region from Singapore and in Japan from Tokyo. In fiscal year 2002 (ending September), the company achieved sales of Euro 5.21 billion with about 30,400 employees worldwide. Infineon is listed on the DAX index of the Frankfurt Stock Exchange and on the New York Stock Exchange (ticker symbol: IFX). Further information is available at http://www.infineon.com.
Information Number
INFCPR200309.130