Infineon Introduces Next Generation Unified Processor Core Architecture; TriCore 2 Boosts Performance of Innovative Compute Engine for Embedded Applications
The principal enhancement to the core architecture is a new six-stage superscalar processor pipeline, which supports clock rates of 600 MHz in SoC devices manufactured in 0.13 micron process technology. The new core maintains key design characteristics from earlier versions of the Tricore architecture, including a focus on providing usable processor bandwidth through task switching efficiency, overall processor efficiency and a small die area for the core.
The expected processing performance of the Tricore 2 core is 900 MIPS when operating at 600 MHz. When implemented in Infineons 0.13 micron technology, the core will occupy approximately 2 mm² . A system implementation, including the core, memory management unit, 192 Kbyte memory, and interfaces for co-processor and external devices, will occupy less than 7 mm² .
The success of the first versions of theTriCore core presented a tough challenge to our architecture and product engineering teams. TriCore 1.x has won designs in systems from automotive engine control to wireless terminals, as well as in network processing, industrial machine control systems and data storage controller designs, said Tony Webster, Vice President of the Cores & Modules Group at Infineon Technologies. By defining a new core that maintains all of the strength of the current architecture, while tripling the potential operating frequency, we have created a new member of the TriCore product family that provides system designers with greater flexibility to produce innovative solutions for advanced embedded systems.
The TriCore Unified Processor core is well suited for applications that previously required separate MCU and DSP components. Current versions of the core are implemented in more than a dozen processor designs, including six publicly announced and shipping application specific standard products (ASSPs) designed for Infineon customers. These applications span a range of high-growth market and application categories, including chips for both fixed base stations and mobile terminals for next generation cellular, data storage ICs, integrated access devices for broadband networks, industrial control and automotive engine management.
Meeting the Performance Challenge
In a presentation today at the Embedded Processor Forum (San Jose, Calif.) Infineon described the underlying design principles for TriCore 2. The core implements a superset of the instruction set architecture of TriCore 1.x. While maintaining the balanced system performance and task switching efficiency that distinguishes TriCore from other hybrid CPU/DSP systems, the principal goal was to push operating frequency to the levels required in future system designs. To accomplish this, Infineon implemented a six-stage pipeline, compared to the four stage pipeline of the first TriCore core.
Longer pipelines typically reduce the number of instructions per cycle (IPC), which is the most direct measure of a processors efficiency. Another challenge raised by the lengthened pipeline is the ability for program code from earlier implementations to operate in the new environment. To reduce pipeline effects, the TriCore 2 architecture implements techniques to reduce branching latency, couples load and integer pipes to improve instruction flow, and writes data to target buffers to reduce load stalls. These techniques yield improved efficiency and serve to make the pipeline appear to instruction code as nearly identical to TriCore 1. As a result, the overall efficiency of TriCore 2 matches that of the earlier core, at approximately 1.5 IPC.
The TriCore 2 architecture also implements a 64-bit wide cross bar interface, enhancing the ability to operate at maximum frequency and achieve high concurrent bandwidth between the core, coprocessor and peripheral systems. The high-speed cross bar is inherent to the modular design philosophy followed in the core. Interfaces to multiple external memory banks, coprocessors or complimentary cores are separated from the system bus. Additionally, memory systems can be operated without specific reference to bus timing and protocol.
Infineon plans to make the TriCore 2 architecture available for designs in the first half of 2002, and the company and its third-party tool partners plan to release development and evaluation tools beginning in early 2002. The new core, like the currently available TriCore 1.x cores, will also be made available in soft macro form for licensing to qualified parties.
Infineon Technologies AG, Munich, Germany, offers semiconductor and system solutions for applications in the wired and wireless communications markets, for security systems and smartcards, for the automotive and industrial sectors, as well as memory products. With a global presence, Infineon operates in the US from San Jose, CA, in the Asia-Pacific region from Singapore and in Japan from Tokyo. In the fiscal year 2000 (ending September), the company achieved sales of Euro 7.28 billion with about 29,000 employees worldwide. Infineon is listed on the DAX index of the Frankfurt Stock Exchange and on the New York Stock Exchange (ticker symbol: IFX). Further information is available at www.infineon.com