Memories for Embedded Systems

Infineon offers a HyperBus Master Interface Controller IP Package to our qualified customers and partners. The IP Package is a collection of RTL (Register-transfer level) source code and documentation intended to help designers add support for HyperBus to their FPGA (Field-Programmable Gate Array), ASIC (Application-Specific Integrated Circuit), or ASSP (Application-Specific Standard Product) host controller platform. The Controller IP is offered free of charge and is royalty-free (see "HyperBus Interface Materials End User License Agreement" for full details). The Controller IP supports both HYPERFLASH™ and HYPERRAM™ products.

The HyperBus Master Interface Controller IP Package includes the following software and materials:

• HyperBus Controller Verilog HDL RTL Source Code
• HyperBus Controller IP Specification
• System Verilog Test Bench (AXI4 and AXI3)
• Verilog Memory Behavioral Model (HYPERFLASH™ and HYPERRAM™)
• Test Specification
• Test (Verification Report)
• Test Script
• Application Note for AMBA AXI