At a glance

This role involves working on synthesis, floor and power plan, place and route, clock tree synthesis, DFY, DFM timing closure for complex designs and work along with SOC design methodology, Flow and Implementation Engineers within Design Engineering Services team.

Quick info

Location Bangalore
Entry level Professionals / experienced
Job ID 21774
Start Oct 31, 2017
Type Full time
Contract Permanent

Job description

In your new role you will: 
  1. Full chip Implementation from netlist to GDSII, physical verification, timing closure and signoff extraction.
  2. Physical partitioning, floorplan, powerplan and Place and Route for low power/high performance designs.
  3. Develop innovative solutions to fix critical issues in the design.
  4. Develop efficient Clock Tree to achieve better Quality of Results and achieve timing closure with minimum eco cycles.
  5. Work closely with Timing methodology/signoff team to improve physical implementation flow which helps faster timing closure.
  6. Getting deeper into major technical issues and help to resolve design issues. Support flow team to make flow updates which impacts larger community.
  7. Project management for SoC implementation and methodology projects.
  8. Responsible for project deliveries of SoC implementation projects.
  9. Introduce best project management practices for methodology and SoC implementation projects.Responsible for project schedule planning, resource planning, defining delivery milestones, tracking designs teams across various sites. schedule and customer interfacing.

Profile

You are best equipped for this task if you have:
  • BE / BTech / MS in Electronics with 8-12 years experience.
  • Managed/Worked on multiple tapeouts at 90nm/65nm/40nm/28nm/16nm nodes complex designs.
  • Working (hands on) knowledge on place & route, synthesis and STA for full chip complex designs.
  • Strong experience in P&R, timing closure, synthesis, constraining and timing analysis required.
  • Experience in Automotive and Industrial domain designs is desirable.
  • Experience in low power/multi voltage design and understanding/development of UPF is a must.
  • Excellent debugging skills to diagnose and devise workarounds for flow/design issues.
  • Deep knowledge of Synopsys tools and flow is a must.
  • Perl and TCL/TK required to achieve highly automated, reproducible and fast results.
  • Knowledge about data management is a definite plus.
  • Good team player working with geo-dispersed cross cultural and cross functional teams.
  • Good communication and interpersonal skills required.

About Us

Energy Efficiency - Mobility - Security - INFINEON

Our global team, with over 34.000 employees, works to improve energy efficiency, enables new mobility concepts and provides for security in our digital age. With our innovative semiconductors and system solutions we contribute to a more sustainable future.

Was wir Ihnen in Bangalore bieten