The SysClk_PDL Component provides an interface to the programmable peripheral clock dividers. It allows you to configure the dividers by specifying a frequency with tolerance, or by specifying a divider.
- Generates programmable clock dividers for use with other Components that require clocks
- 8 bit, 16 bit, 16.5 bit and 24.5 bit dividers available
- Configure clock by specifying frequency, or divider value
- Specify frequency tolerance for clock
- Phase align with another programmable clock divider