3 2 1
+ + =
As thewhole cycle takes 300s, the entire operational lifetime is accordingly 12583h.
The lifetime in this example is thus limited by the bond wire connections which show a
lifetimeof approximately 60%of the lifetime of the system solder layer.
14.7 Failure images
Failuresmay occur during themanufacture and operation of power semiconductors and
power modules. Below are some pictures of defects, which have either caused such
failures or were the result. The failure images depicted have been produced in the
laboratory to show clearly the specific fault mechanism. In a real application, these
failure patterns, however, can often not be identified so clearly. On the one side, several
failure patterns might be superimposed, or, the degree of destruction is such that
identification is no longer possible. Therefore a lot of experience and routine is required
when evaluating real failure images, inorder to come upwith the correct result.
14.7.1Failure imagesof process engineeringandmechanics
depicts different results after the bond process.
shows a bond
without a fault as a reference, whilst
show flawed bonds.
These defects canbe detected by optical ormechanical checks duringproduction.
Deformation of thebond foot
Another variant of a fault during the bonding process is depicted i
bond wire has dislodged itself from the chip directly after the bonding process and
removed theuppermetallisation layer aswell.