reference value. The output of the comparator represents the digital output signal of the
-ADC. This signal is then fed via an internal 1-bit digital-analogue converter (DAC)
back to the summing stage, where it is subtracted from the original input signal and
forwarded to the digital filter and decimator. The analogue input signal is sampled at
very high frequency – a process known as oversampling. The serial 1-bit output signal
-ADC contains a sequence comprising logically, "0" and "1". For an input
signal of 0V, the digital output signal will have the same number of "0" as "1". If the input
signal increases, the proportion of "1" in the
data stream increases. Conversely, if
the input signal is negative, "0" will predominate in the data stream. The chronological
mean valueof the output signal is therefore indirect proportion to the input signal.
first and second order ADC
The operatingprinciple of an
-ADC is described below.
An analogue-digital converter samples the input signal with n-bit
resultingquantisation error due to samplingand the subsequent conversion into discrete
values is 0.5 LS
. An error signal, possibly also noise, is now superimposed on the
LSB= least significant bit, and describes the lowest possible resolution for abit duringquantisation q.