IGBT Modules - Technologies, Driver and Application (Second Edition) - page 404

Fig. 11.27
Conductor output voltageU
of a two- and three-level inverter
Amulti-level inverter can be designed in different variants.
shows a design
of a three-level inverter, in which the centre point of the DC-bus capacitors and the
diodes D
and D
operates as a reference or neutral point. In this circuit topology the
semiconductors used are exposed to amaximum of only half the DC-bus voltage (plus
switching over-voltages). Because of the circuit design, this variant is referred to as
Neutral Point Clamped (NPC), Diode ClampedMulti-Level (DCML) or Neutral Clamped
Multi-Level (NCML) inverter. A similar topology is depicted in
, in which no
fixed reference point is defined. Instead, the resulting voltages will be floating or "flying"
in reference to the DC-bus voltage. Accordingly, the name Flying Capacitor Multi-Level
(FCML) inverter was given.
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