IGBT Modules - Technologies, Driver and Application (Second Edition) - page 403

or IGBT5. The signals for the bottom IGBT4, IGBT6 and IGBT2 are created by inverting
the control signals of the upper IGBTs
Due to the PWM control the DC-bus voltage is switched to themotor phases according
to the pulse pattern
shows the phase voltage VM1 in the diagram below
right). The square-wave, but sine-weighted voltage causes a sinusoidal current together
with themotor inductance, as is depicted in
ottom left for all three phases.
An improvement, i.e. a better fit to an ideal sinewave of themotor currents is achieved,
for example, by increasing the switching frequency, which has been selected rather low
at 1kHz for illustrative reason.
11.4.2Multi-level inverter
Standard voltage source inverters, as described in chapter
are also known as
two-level inverters, as they switch their respective output to the centre of the DC-bus
between two voltage levels
). For a three-level inverter, the output can take
three different voltage levels
Accordingly, inmulti-level inverterswith n levels, n different voltage levels can appear at
the output. In practice, however, only very rarely are inverters with more than three
voltage levels used, so that in the following only the three-level inverter will be examined
more closely
depicts the output voltages of the respective phases relative to
the centre of theDC-bus both for the two-level and for the three-level inverter. The inter-
linking conductor voltage (in this example U
) is made up of the difference of the two
phase voltages (U
and U
). The aim of the PWM control of the IGBTs in a two-level
or three-level inverter is to generate the fundamental of the desired sinusoidal output
voltage or current with as little interfering harmonics as possible. Comparing
quantitatively the phase voltages U
of the two-level and three-level inverter with each
other, it can be seen that the three-level inverter more closely resembles the shape of
the sine. This can also be proven with a frequency analysis, so that the lesser
proportionof distortion is oneof thebenefits of the three-level inverter.
The dead time or interlock delay time between the drive signals of the upper and lower section, necessary in a
real application, is not taken into account in this simulation.
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