TriCore™ Architecture & Core

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TriCore™ Architecture & Core

Evolution of TriCore™ Generations

AURIX™ is Infineon’s brand new family of microcontrollers serving exactly the needs of the automotive industry in terms of performance and safety. Its innovative multicore architecture, based on up to three independent 32-bit TriCore™ CPUs, has been designed to meet the highest safety standards whil significantly increasing performance at the same time. Using the AURIX™ platform, automotive developers will be able to control powertrain and safety applications with one single MCU platform. Developments using AURIX™ will require less effort to achieve the ASIL-D standard than with a classical Lockstep architecture. Customers wanting to reduce their time-to-market can now cut down their MCU safety development by 30%. By the same token, a performance surplus of 50% up to 100% allows for more functionality and offers a sufficient resource buffer for future requirements, keeping the power consumption on the single-core microcontroller level. While protecting IP, and preventing theft and fraud, AURIX™ provides an already built-in Hardware Security Module. With its special feature set, AURIX™ is the perfect match for powertrain applications (including hybrid and electrical
vehicles) as well as safety applications (such as steering, braking, airbag and advanced driver assistance systems).

TriCore™ 1.3

TriCore™ 1 is the first single-core 32-bit microcontroller-DSP architecture optimized for real-time embedded systems. TriCore™ unifies the best of 3 worlds - real-time capabilities of microcontrollers, computational prowess of DSPs, and highest performance/price implementations of RISC loadstore architectures. The Instruction Set Architecture (ISA) supports a uniform, 32-bit address space, with optional virtual addressing and memory-mapped I/O. It allows for a wide range of implementations, ranging from simple scalar to superscalar. Furthermore, the ISA is capable of interacting with different system architectures, including those with multiprocessing. This flexibility at the implementation and system levels allows for different trade-offs between performance and cost at any point in time. To support TriCore™ implementations with 32-bit instructions and simplified instruction fetching, the entire architecture is represented in 32-bit instruction formats. In addition, the architecture includes 16 bit instruction formats for the most frequently occurring instructions. These instructions significantly reduce code space, lowering memory requirements, system cost, and power consumption. Real-time responsiveness is largely determined by interrupt latency and context-switch time. The high-performance architecture minimizes interrupt latency by avoiding long multicycle instructions and by providing a flexible hardware-supported interrupt scheme. Furthermore, the architecture supports fast context switching.

Feature Overview:

  • 32-bit architecture

  • 4-GByte virtual or physical data, program, and input/output address spaces

  • Full-featured memory management system

  • 16-/32-bit instructions for reduced code size

  • Low interrupt latency

  • Fast automatic context switching

  • Multiply-accumulate unit

  • Saturating integer arithmetic

  • Bit handling

  • Packed data operations

  • Zero-overhead loop

  • Byte and bit addressing

  • Little-endian byte ordering

  • Flexible interrupt prioritization scheme

  • Memory protection

  • Debug support

  • Flexible power management



TriCore™ 1.6




Feature Overview:

  • Up to 300MHz
  • Six-stage pipeline
  • Dedicated integer division unit in hardware
  • Optimized Floating Unit (FPU)
  • Enhanced branch prediction (branch history and target bufflers)
  • Optimized crossbar interconnect with 64-bit data width (shared resource interconnect)
  • 16-bit and 32-bit instruction formats
  • 32-bit load-store Harvard architecture
  • Superscalar execution
  • Sustained throughput by dual 16x32 MACs
  • SIMD (Single Instruction Multiple Data) packed arithmetic
  • Zero overhead loops (loop recognition buffer)
  • DSP addressing modes and saturated math


  • Highest performance for complex engine management systems
  • Integrated MCU-DSP instructions in one core
  • Very fast context switching for interrupt driven system
  • Fast and efficient processing of multiple tasks on one engine
  • Low code size and inherent high level language support
  • One development toolset for both MCU and DSP tasks
  • Higher flexibility and lower cost
  • Support ans supply of complete system chipset




TriCore™ Architecture & Core Subcategories

TriCore™ Architecture & Core

Product Brief

Title Size Date Version
135 KB 07 Feb 2011 01_00

User Manual

Title Size Date Version
7.7 MB 07 Feb 2011
320 KB 07 Feb 2011 01_01
3.3 MB 07 Feb 2011
290 KB 07 Feb 2011 01_01
2.4 MB 03 Jan 2012
8.6 MB 03 Jan 2012
225 KB 23 Nov 2009
1.1 MB 07 Feb 2011
4.3 MB 06 Aug 2007 01_02
1.5 MB 07 Feb 2011 01_04
714 KB 07 Feb 2011 02_03
7 MB 11 May 2012 01_00
10.6 MB 14 May 2012 01_00

Application Notes

Title Size Date Version
316 KB 07 Aug 2007 01_01
348 KB 06 Aug 2007 01_01
331 KB 07 Aug 2007 01_01
263 KB 07 Aug 2007 01_00
642 KB 07 Feb 2011 01_00
1.1 MB 07 Feb 2011 01_00

TriCore™ Architecture & Core

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