Infineon Describes Innovative Memory Circuits at ISSCC 2006

San Francisco. Calif. – February 6, 2006 – This week at the ISSCC 2006 (IEEE International Solid-State Circuits Conference) in San Francisco, Infineon Technologies AG (FSE/NYSE: IFX) is presenting three papers that describe innovations in CMOS-based memory for computing and graphics applications. The technical papers, highlighting the company’s know-how in advanced chip design, describe ICs now in use or soon to be available for market applications.  In addition, Infineon will participate in a forum addressing the requirements and implementation choices for high-speed interfaces in chip-to-chip applications.

In a Graphics DRAM paper, Infineon researchers will report on methods to reach higher performance levels in a mass market chip designed to better handle multimedia applications.  The second paper describes an Advanced Memory Buffer (AMB) that is used with standard DRAM to build high-density, high-speed memory modules for computers and servers.  The third paper describes a high-performance transceiver architecture that implements a novel clock distribution scheme to support future AMB-based memory modules.

Advanced Graphics DRAM

Multimedia applications in desktop and portable computers require increasingly greater performance from the memory chips used on graphics cards.  In Session 8.2 at 9:00 a.m. on Tuesday, Feb. 7, Infineon researchers will present “A 2Gb/s/pin 512Mb Graphics DRAM with Noise-Reduction Techniques.” This paper reports on an 8-bank 512Mb DRAM that operates at up to 2Gbps, achieving its high data rate by use of advanced noise reduction techniques that improve I/O (input/output) behavior and internal signaling.  This GDRAM exceeds the performance of similar previously published devices by 25 percent, while still using a conventional, non-differential memory interface and conventional DRAM process technology.

New Technology for High-Speed Memory Modules

Computer servers, which require the highest possible memory density and performance, represent an important and very challenging market for the DRAM industry.  This has led to the development of the Fully Buffered DIMM (FB-DIMM), a memory module that can host up to 36 DRAM chips and communicates with a host processor through an AMB (Advanced Memory Buffer). The DRAM on the module interfaces with an AMB using standard DDR methods, and the AMB sends data to and receives data from the host processor or a neighboring FB-DIMM by means of a technique called differential point-to-point signaling. 

In Session 18.6, “Data Recovery and Retiming for 4.8Gb/s Fully Buffered DIMM Serial Links,” at 4:15 PM on Tuesday, Feb. 7, Infineon researchers describe the serial link data recovery and retiming implementation details of a CMOS AMB that comprises 24 serial links, a core processing unit, and a DDR interface.  Because the AMB supports an 800Mbps DDR2 data rate, the links operate at speeds up to 4.8Gbps.  Overall, the described AMB achieves an experimental input sensitivity of 50mVpp at a BER (bit error rate) of 10 ^-12, exceeding the specified requirement of 170mVpp at a BER of 10 ^-12.

In Session 4.5, “A 100mW 9.6Gb/s Transceiver in 90nm CMOS for Next-Generation Memory Interfaces,” at 3:45 PM on Monday, Feb. 6, Infineon researchers give an insight into new architectures being developed for the next generation of AMB-based FB-DIMMs.  The transceiver presented implements a forwarded clock architecture that meets the need for power-efficient clock distribution to each individual data receiver in an FB-DIMM.

To provide more information on the background of the FB-DIMM technology, Infineon will also be giving a presentation in Session F5, High Speed Interconnect, “The Evolution of High-Speed Interfaces into Memory Applications,” in the Circuit Design Forum at 10:00 AM on Thursday, Feb. 9.

Further information on Infineon’s portfolio of memory products is available at www.Infineon.com/memory.