Infineon Demonstrates Next Generation Chip Structures: A First Step Towards Manufacturing Future Chip Features with Next Generation Lithography

Nov 12, 2002 | Technology Media

Munich/Germany, November 12, 2002 - Infineon Technologies (FSE/NYSE: IFX) today announced, that its researchers have demonstrated the patterning of thin dielectric films on silicon wafers utilizing a resist mask patterned by Extreme Ultra Violet (EUV) Lithography. This R&D result marks an important milestone and shows that the shrink roadmap for critical dimensions of microchips within this decade appears to be realistic after having used EUV radiation and plasma etching for fabricating nano grooves as base structures for advanced chip metallizations.

The EUV lithography of the etched wafers was performed by Infineon at the Sandia National Laboratories, Livermore. Patterns were generated by an early EUV R&D exposure system in a 120 nm thin experimental resist provided by Shipley. Infineon researchers successfully transferred these patterns into the underlying dielectric film without loosing resolution. The grooves etched into the dielectric film by a plasma etching process are ranging down to about 60 nm in width.

The fabricated nano grooves are the base structure for modern chip metallization. In the so called damascene technique - named after the way ornaments were once applied in damascene swords - they are filled with metal. After complete removal of all metal covering the surface by chemical mechanical polishing small metal lines are realized. Such metal lines are being used for high speed interconnects in progressive integrated circuits.

The results from Infineon's researchers demonstrate the feasibility of EUV thin film imaging and integration and mark an important step towards sub–50nm structures. It verifies that plasma etching tools and processes will be ready for pattern transfer when EUV manufacturing tools will be available for defining damascene groove patterns for the 65nm technology node. The International Technology Roadmap for Semiconductors (ITRS) predicts this node to be in volume-production from 2007 on. The ITRS which extends to 2016 describes the technological and material demands of future chip generations. However, today the time schedules of semiconductor manufacturers are tighter than those of the ITRS.

“Next Generation Lithography is such an important task, that we spent a lot of resources on the development of this high sophisticated technology,” said Dr. Soenke Mehrgardt, CTO of Infineon Technologies. “Demonstrating already today the fabrication of the base structures for 65nm metallization utilizing EUV lithography for pattern definition is an important step on our aggressive shrink roadmap over the next decade, offering our customers higher performance, more cost effective and extremely high integrated chips.”

Lithography is an indispensable technique for producing microelectronic products. As the features on integrated circuits have become smaller and smaller, lithographic methods have been more and more refined. Traditional optical technologies will reach their final phase as feature sizes - much smaller than the wavelength of the used light sources - need to be printed. Thus, even with expensive enhancement techniques the current light-optical methods will reach their physical limits. This also implies that alternative technologies have to be developed to face the challenges of the next chip generations.

Lithography tools needed for manufacturing chip generations with feature sizes of 60 nm and below are under intensive development. EUV lithography is the main stream candidate for these dimensions. The EUV technology uses extreme ultraviolet wavelengths as small as 13.5 nm, far below the wavelengths of traditional optical light sources.

The EUV-LLC, a consortium of semiconductor chip manufacturers consisting of AMD, IBM, Infineon, Intel, Micron, and Motorola is jointly developing EUV lithography at several US National Laboratories, including the Sandia National Laboratories. The plasma etching processes performed for pattern transfer from resist to underlying layers on the silicon wafers were run in the NanoLab of Infineon´s Research Department in Munich using today’s state-of-the-art semiconductor manufacturing equipment without any modifications. The results reported are based on a project sponsored by the German Ministry for Education and Research.

About Infineon

Infineon Technologies AG, Munich, Germany, offers semiconductor and system solutions for the automotive and industrial sectors, for applications in the wired communications markets, secure mobile solutions as well as memory products. With a global presence, Infineon operates in the US from San Jose, CA, in the Asia-Pacific region from Singapore and in Japan from Tokyo. In the fiscal year 2002 (ending September), the company achieved sales of Euro 5.21 billion with about 30,400 employees worldwide. Infineon is listed on the DAX index of the Frankfurt Stock Exchange and on the New York Stock Exchange (ticker symbol: IFX). Further information is available at

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    Infineon Demonstrates Next Generation Chip Structures: A First Step Towards Manufacturing Future Chip Features with Next Generation Lithography
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