Infineon introduces configurable CARMEL DSP Core for 3G wireless and broadband communication applications

Mar 27, 2000 | Technology Media

Munich/Germany – March 27, 2000 – As a major step in reinforcing its position in 3G (third generation) wireless and broadband connectivity products, Infineon Technologies today announced the second generation 16-bit, fixed-point CARMEL™ DSP core. The 20xx core features PowerPlug™ accelerators that enable SoC developers to configure the instruction set as well as to modify the core. As a result the PowerPlug™ accelerator can implement computation-intensive features such as multiple data rates and complex modulation schemes without compromising power dissipation and system costs.

With Infineon’s PowerPlug™ modules, system designers can accelerate the execution of application-specific functions to boost DSP performance by reconfiguring the DSP core. The PowerPlug™ modules are tightly coupled to the CARMEL™ DSP core and are viewed by the software as built-in execution units of the DSP datapath. Their addition results in scalability across hardware and software and optimization of cost and performance.


“The PowerPlug™ technology combines the price/performance benefits of ASIC design with the flexibility of a programmable DSP,” said Shaul Berger, vice president of Infineon Technologies’ DSP Cores. “CARMEL™ DSP 20xx core’s scalable architecture allows our customers to offer cost-competitive 3G wireless and broadband products faster to market.”


The core’s instruction set is a superset of the first generation CARMEL™ DSP 10xx core, featuring the CLIW™ (Configurable Long Instruction Word) architecture. The CLIW™ technology combines the benefits of the VLIW’s high performance and flexible control and SIMD’s (Single Instruction Multiple Data) compact code and low power, without the associated penalty in code size and power dissipation usually found in VLIW architectures.


The CARMEL™ DSP 20xx core initially provides for frequencies up to 300 MHz. Through the PowerPlug™ extensions, the new core’s code-efficient DSP MIPS can double the performance of the native core without compromising power dissipation. The additional processing power made available by the PowerPlug™ technology meets the requirements for faster data transfer rates and the convergence of voice, data and video over wireless and broadband applications. The CARMEL™ DSP 20xx core features energy-efficient DSP MIPS to extend battery life and support memory power saving mechanisms, enabling new mobile applications users to take advantage of 3G services.


The CARMEL™ DSP 20xx core will be available in the fourth quarter 2000.

For information on Infineon’s CARMEL™ DSP architecture and tools visit www.infineon.com/dspwww.infineon.com/dsp.


About Infineon



Infineon Technologies AG, Munich, Germany, offers semiconductor solutions for applications in the wireless and wired communications markets, for the automotive and industrial sectors, for security systems and chip cards as well as memory products. With a global presence, Infineon operates in the US from San Jose, CA, and in the Asia-Pacific region from Singapore. In the fiscal year 1999 (ending September), the company achieved sales of Euro 4.24 billion (US $ 4.51 billion) with about 26,000 employees worldwide. Further information at www.infineon.com


Infineon, the stylized Infineon Technologies design, CARMEL, PowerPlug and CLIW are trademarks and servicemarks of Siemens AG. All other trademarks are the property of their respective owners. Any statements in this document that are not historical facts are forward-looking statements that involve risks and uncertainties; actual results may differ from the forward-looking statements. Infineon Technologies AG undertakes no obligation to publicly release the results of any revisions to these forward-looking statements that may be made to reflect events or circumstances after the date hereof or to reflect the occurrence of unanticipated events.

Information Number

INFCMD200003.050e

Press Photos

  • Infineon Technologies Carmel 20xx Architecture, Block Diagram of PowerPlug Module Interface.
    Infineon Technologies Carmel 20xx Architecture, Block Diagram of PowerPlug Module Interface.
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